diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-04-11 21:21:35 +0200 |
|---|---|---|
| committer | Jakub Czapiga <jacz@semihalf.com> | 2023-04-13 05:53:25 +0000 |
| commit | 915c3878043752359a4f1b1a1fabb39e0eb3ed7d (patch) | |
| tree | 2f6022e7cf74b66fbba4442e8ef72be67034bbb5 /src/soc | |
| parent | 4d8a352c5a9541cfce059269388a22216f3c24af (diff) | |
soc/amd/stoneyridge/northbridge: use common acpi_fill_root_complex_tom
Use the common acpi_fill_root_complex_tom function instead of the SoC-
level northbridge_fill_ssdt_generator function that does basically the
same.
TEST=Resulting coreboot SSDT remains unchanged on Careena.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie0f100e0766ce0f826daceba7dbec1fb88492938
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/stoneyridge/northbridge.c | 24 |
1 files changed, 2 insertions, 22 deletions
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 7913827cd2..b1d2bdda46 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> +#include <amdblocks/acpi.h> #include <amdblocks/biosram.h> #include <amdblocks/hda.h> #include <device/pci_ops.h> @@ -186,27 +187,6 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) return (unsigned long)current; } -static void northbridge_fill_ssdt_generator(const struct device *device) -{ - msr_t msr; - char pscope[] = "\\_SB.PCI0"; - - acpigen_write_scope(pscope); - msr = rdmsr(TOP_MEM); - acpigen_write_name_dword("TOM1", msr.lo); - msr = rdmsr(TOP_MEM2); - /* - * Since XP only implements parts of ACPI 2.0, we can't use a qword - * here. - * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt - * slide 22ff. - * Shift value right by 20 bit to make it fit into 32bit, - * giving us 1MB granularity and a limit of almost 4Exabyte of memory. - */ - acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); - acpigen_pop_len(); -} - static unsigned long agesa_write_acpi_tables(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp) @@ -285,7 +265,7 @@ struct device_operations stoneyridge_northbridge_operations = { .set_resources = set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .acpi_fill_ssdt = northbridge_fill_ssdt_generator, + .acpi_fill_ssdt = acpi_fill_root_complex_tom, .write_acpi_tables = agesa_write_acpi_tables, }; |