diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2022-06-08 21:41:53 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-20 12:06:56 +0000 |
| commit | 9088b681f539873e70a8904ca41165f3e830232f (patch) | |
| tree | 2454d6d4ecd3c11dd87a9d0f516725cd25632d6c /src/soc | |
| parent | ae64b6e5db2e35b45e76ee4ef9ec416a6f09384e (diff) | |
soc/intel/apollolake: Hook up UfsEnabled to devicetree
Hook up FSP S UfsEnabled UPD (1d.0) to devicetree.
UFS only exist on GLK, and has been there since its
initial releases.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1976bfd340c728c64aaf36d296ac41dcd47bfc61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/pci_devs.h | 4 |
2 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index bab39bb4b6..20bbde9288 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -449,6 +449,9 @@ static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig) case PCH_DEVFN_CNVI: silconfig->CnviMode = 0; break; + case PCH_DEVFN_UFS: + silconfig->UfsEnabled = 0; + break; #endif case PCH_DEVFN_HDA: silconfig->HdaEnable = 0; diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index 9dbc11c3d6..cc31370d93 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -148,6 +148,10 @@ #define PCH_DEVFN_EMMC _PCH_DEVFN(EMMC, 0) #define PCH_DEV_EMMC _PCH_DEV(EMMC, 0) +#define PCH_DEV_SLOT_UFS 0x1d +#define PCH_DEVFN_UFS _PCH_DEVFN(UFS, 0) +#define PCH_DEV_UFS _PCH_DEV(UFS, 0) + #define PCH_DEV_SLOT_SDIO 0x1e #define PCH_DEVFN_SDIO _PCH_DEVFN(SDIO, 0) #define PCH_DEV_SDIO _PCH_DEV(SDIO, 0) |