diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-06-06 08:14:57 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-06-16 19:54:49 +0000 |
| commit | 8c9a89de9961e7029835e987cb0f705b7efa77a7 (patch) | |
| tree | f0840d70ad26d96c43aa8bcfde47d0727663cefe /src/soc | |
| parent | d614e85418c1fb524df34bb7522ccd6b410296a1 (diff) | |
arch/x86/ioapic: Drop irq_on_fsb as a configurable item
APIC Serial Bus pins were removed with ICH5 already, so a choice
'irq_on_fsb = 0' would not take effect. The related register BOOT_CONFIG
0x3 is also not documented since ICH5.
For emulation/qemu-q35 with ICH9 the choice INTERRUPT_ON_APIC_BUS was
wrong and ignored as BOOT_CONFIG register emulation was never implemented.
For ICH4 and earlier, the choice to use FSB can be made based on the
installed CPU model but this is now just hardwired to match P4 CPUs of
aopen/dxplplusu.
For sb/intel/i82371eb register BOOT_CONFIG 0x3 is also not defined
and the only possible operation mode there is APIC Serial Bus, which
requires no configuration.
Change-Id: Id433e0e67cb83b44a3041250481f307b2ed1ad18
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55257
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/broadwell/pch/lpc.c | 6 | ||||
| -rw-r--r-- | src/soc/intel/common/block/lpc/lpc_lib.c | 6 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/lpc.c | 6 |
3 files changed, 0 insertions, 18 deletions
diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index f62394b4b9..10cc9d8c60 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -42,12 +42,6 @@ static void pch_enable_ioapic(struct device *dev) reg32 |= 0x00270000; io_apic_write(VIO_APIC_VADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); } static void enable_hpet(struct device *dev) diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 49509409e0..1b6936e508 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -290,12 +290,6 @@ void pch_enable_ioapic(void) reg32 |= (redir_entries - 1) << 16; io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); } static const uint8_t pch_interrupt_routing[PIRQ_COUNT] = { diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 65be16e302..a099c31f2b 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -42,12 +42,6 @@ static void pch_enable_ioapic(struct device *dev) reg32 |= (PCH_LP_REDIR_ETR - 1) << 16; io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32); - - /* - * Select Boot Configuration register (0x03) and - * use Processor System Bus (0x01) to deliver interrupts. - */ - io_apic_write((void *)IO_APIC_ADDR, 0x03, 0x01); } /* interrupt router lookup for internal devices */ |