summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2021-06-23 16:51:16 +0200
committerAngel Pons <th3fanbus@gmail.com>2022-08-14 10:53:47 +0000
commit865c97c304af61903f3fad7d489db5097255fe11 (patch)
tree6553ab5a609e46ab583253af86abd0ad13e33568 /src/soc
parent4a8cb30222a34de760d38c7d13d54e24221d9fec (diff)
broadwell: Decouple LPDDR3 DQ/DQS maps from `pei_data`
Introduce the `BROADWELL_LPDDR3` Kconfig option along with some wrapper code to allow mainboards using LPDDR3 DRAM to supply the DQ/DQS maps to chipset code without having to use `pei_data`. The only mainboard using LPDDR3 is Google Samus. Change-Id: I0aaf0ace243c03600430c2a7ab6389a7b20cb432 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55812 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/broadwell/Kconfig6
-rw-r--r--src/soc/intel/broadwell/include/soc/pei_wrapper.h8
-rw-r--r--src/soc/intel/broadwell/raminit.c7
3 files changed, 21 insertions, 0 deletions
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 4b4df52bf3..3a5b5d52c1 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -13,6 +13,12 @@ config SOC_SPECIFIC_OPTIONS
select MRC_SETTINGS_PROTECT
select REG_SCRIPT
+config BROADWELL_LPDDR3
+ bool
+ help
+ Selected by mainboards using LPDDR3 DRAM to supply mainboard-specific
+ LPDDR3 DQ and DQS CPU-to-DRAM mapping info needed to perform raminit.
+
config ECAM_MMCONF_BASE_ADDRESS
default 0xf0000000
diff --git a/src/soc/intel/broadwell/include/soc/pei_wrapper.h b/src/soc/intel/broadwell/include/soc/pei_wrapper.h
index 80222beccd..cf85c044be 100644
--- a/src/soc/intel/broadwell/include/soc/pei_wrapper.h
+++ b/src/soc/intel/broadwell/include/soc/pei_wrapper.h
@@ -33,9 +33,17 @@ struct spd_info {
unsigned int spd_index;
};
+struct lpddr3_dq_dqs_map {
+ uint8_t dq[2][6][2];
+ uint8_t dqs[2][8];
+};
+
/* Mainboard callback to fill in the SPD addresses */
void mb_get_spd_map(struct spd_info *spdi);
+/* Mainboard callback to retrieve the LPDDR3-specific DQ/DQS mapping */
+const struct lpddr3_dq_dqs_map *mb_get_lpddr3_dq_dqs_map(void);
+
void broadwell_fill_pei_data(struct pei_data *pei_data);
void mainboard_fill_pei_data(struct pei_data *pei_data);
diff --git a/src/soc/intel/broadwell/raminit.c b/src/soc/intel/broadwell/raminit.c
index 686c782e2e..d088e5145c 100644
--- a/src/soc/intel/broadwell/raminit.c
+++ b/src/soc/intel/broadwell/raminit.c
@@ -196,6 +196,13 @@ void perform_raminit(const struct chipset_power_state *const power_state)
mainboard_fill_pei_data(&pei_data);
+ if (CONFIG(BROADWELL_LPDDR3)) {
+ const struct lpddr3_dq_dqs_map *lpddr3_map = mb_get_lpddr3_dq_dqs_map();
+ assert(lpddr3_map);
+ memcpy(pei_data.dq_map, lpddr3_map->dq, sizeof(pei_data.dq_map));
+ memcpy(pei_data.dqs_map, lpddr3_map->dqs, sizeof(pei_data.dqs_map));
+ }
+
/* Obtain the SPD addresses from mainboard code */
struct spd_info spdi = { 0 };
mb_get_spd_map(&spdi);