diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-10-04 15:05:17 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-10-15 23:43:27 +0000 |
| commit | 813462ec31f4bc82488451e371c8d14d388d1e45 (patch) | |
| tree | 6d37c939c0454566ed5caece6f17e1b08106d073 /src/soc | |
| parent | f8bf9a7eaa9c499317ae32704a05634fcef72e0b (diff) | |
amd/stoneyridge: Add function to find PmControl register
Find the PmControl register's I/O address by checking the hardware in
PMx62. Don't rely on the address being the coreboot default. PmControl
is the first register in the AcpiPm1CntBlk.
Change-Id: Ibb608dcaa7801af067d6edd86f92c117c2ac08a6
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 1 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/sb_util.c | 5 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index ebfee2499e..d506af979a 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -202,6 +202,7 @@ u16 smi_read16(u8 reg); u32 smi_read32(u8 reg); void smi_write16(u8 reg, u16 value); void smi_write32(u8 reg, u32 value); +uint16_t pm_acpi_pm_cnt_blk(void); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); void s3_resume_init_data(void *FchParams); int s3_save_nvram_early(u32 dword, int size, int nvram_pos); diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c index 87bff70321..bdb199aa1e 100644 --- a/src/soc/amd/stoneyridge/sb_util.c +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -64,3 +64,8 @@ void smi_write16(uint8_t offset, uint16_t value) { write16((void *)(APU_SMI_BASE + offset), value); } + +uint16_t pm_acpi_pm_cnt_blk(void) +{ + return pm_read16(PM1_CNT_BLK); +} |