soc/amd/picasso: Remove SD controller

Change-Id: Ie9cf361ed0caba9c73727453c4a503557edc854d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

6 files changed, 3 insertions, 64 deletions

diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl
index cdb32cc0d3..cc264e6f85 100644
--- a/src/soc/amd/picasso/acpi/globalnvs.asl
+++ b/src/soc/amd/picasso/acpi/globalnvs.asl
@@ -58,9 +58,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	UT1E,	1,	//        UART1, 12
 	, 2,
 	ST_E,	1,	//        SATA, 15
-	, 8,
-	SD_E,	1,	//        SD, 24
-	, 2,
+	, 11,
 	ESPI,	1,	//        ESPI, 27
 	/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
 	Offset (0x100),
diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
index 8cdb4d2750..206fdfd0e1 100644
--- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
+++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
@@ -53,21 +53,6 @@ Device(SBUS) {
 /* 0:14.3 - LPC */
 #include <soc/amd/common/acpi/lpc.asl>
 
-/* 0:14.7 - SD Controller */
-Device(SDCN) {
-	Name(_ADR, 0x00140007)
-
-	Method(_PS0) {
-		FDDC(24, 0)
-	}
-	Method(_PS3) {
-		FDDC(24, 3)
-	}
-	Method(_PSC) {
-		Return(SDTD)
-	}
-} /* end SDCN */
-
 Name(CRES, ResourceTemplate() {
 	/* Set the Bus number and Secondary Bus number for the PCI0 device
 	 * The Secondary bus range for PCI0 lets the system
@@ -272,15 +257,6 @@ Field( SMIC, ByteAcc, NoLock, Preserve) {
 	offset (0x1e6f), /* USB3 D3 State */
 	U3DS, 3,
 
-	offset (0x1e70), /* SD D3 Control */
-	SDTD, 2,
-	, 1,
-	SDPD, 1,
-	, 1,
-	, 1,
-	SDRT, 1,
-	SDSC, 1,
-
 	offset (0x1e71), /* SD D3 State */
 	SDDS, 3,
 
@@ -421,14 +397,6 @@ Method(FDDC, 2, Serialized)
 				}
 			}
 /* todo			Case(15) { STD0()} */ /* SATA */
-			Case(24) { /* SD */
-				Store(0x00, SDTD)
-				Store(One, SDPD)
-				Store(SDDS, Local0)
-				while(LNotEqual(Local0,0x7)) {
-					Store(SDDS, Local0)
-				}
-			}
 		}
 	} else {
 		/* put device into D3cold */
@@ -482,20 +450,6 @@ Method(FDDC, 2, Serialized)
 				Store(0x03, U1TD)
 			}
 /* todo			Case(15) { STD3()} */ /* SATA */
-			Case(24) { /* SD */
-				Store(Zero, SDPD)
-				Store(SDDS, Local0)
-				while(LNotEqual(Local0,0x0)) {
-					Store(SDDS, Local0)
-				}
-				Store(0x03, SDTD)
-			}
-		}
-		/* Turn off Power */
-		if(LEqual(I0TD, 3)) {
-			if(LEqual(SATD, 3)) {
-				if(LEqual(SDTD, 3)) { Store(Zero, PG1A) }
-			}
 		}
 		if(LEqual(I1TD, 3)) {
 			if(LEqual(I2TD, 3)) {
diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c
index dad9d22e7e..776f328c86 100644
--- a/src/soc/amd/picasso/chip.c
+++ b/src/soc/amd/picasso/chip.c
@@ -100,8 +100,6 @@ const char *soc_acpi_name(const struct device *dev)
 		return "LPCB";
 	case SATA_DEVFN:
 		return "STCR";
-	case SD_DEVFN:
-		return "SDCN";
 	case SMBUS_DEVFN:
 		return "SBUS";
 	case XHCI0_DEVFN:
diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h
index c823fdbfdc..8a885f2c0b 100644
--- a/src/soc/amd/picasso/include/soc/pci_devs.h
+++ b/src/soc/amd/picasso/include/soc/pci_devs.h
@@ -188,11 +188,4 @@
 #define LPC_DEVFN		PCI_DEVFN(PCU_DEV, LPC_FUNC)
 #define SOC_LPC_DEV		_SOC_DEV(PCU_DEV, LPC_FUNC)
 
-/* SD Controller */
-#define SD_DEV			0x14
-#define SD_FUNC			7
-#define SD_DEVID		0x7906
-#define SD_DEVFN		PCI_DEVFN(SD_DEV, SD_FUNC)
-#define SOC_SD_DEV		_SOC_DEV(SD_DEV, SD_FUNC)
-
 #endif /* __PI_PICASSO_PCI_DEVS_H__ */
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index 4392e4f099..0f72a68567 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -303,9 +303,7 @@ typedef struct aoac_devs {
 	unsigned int ut1e:1; /* 12: UART1 */
 	unsigned int :2;
 	unsigned int st_e:1; /* 15: SATA */
-	unsigned int :8;
-	unsigned int sd_e:1; /* 24: SDIO */
-	unsigned int :2;
+	unsigned int :11;
 	unsigned int espi:1; /* 27: ESPI */
 	unsigned int :4;
 } __packed aoac_devs_t;
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index dca3591f85..87b933e119 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -578,7 +578,7 @@ void southbridge_init(void *chip_info)
 
 static void set_sb_final_nvs(void)
 {
-	const struct device *sd, *sata;
+	const struct device *sata;
 
 	struct global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
 	if (gnvs == NULL)
@@ -591,8 +591,6 @@ static void set_sb_final_nvs(void)
 	gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART0);
 	gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART1);
 	/* Rely on these being in sync with devicetree */
-	sd = pcidev_path_on_root(SD_DEVFN);
-	gnvs->aoac.sd_e = sd && sd->enabled ? 1 : 0;
 	sata = pcidev_path_on_root(SATA_DEVFN);
 	gnvs->aoac.st_e = sata && sata->enabled ? 1 : 0;
 	gnvs->aoac.espi = 1;