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authorArthur Heymans <arthur@aheymans.xyz>2022-11-29 18:19:19 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-12-05 14:19:03 +0000
commit759448893c508cd61240b4598336ecdc7f36eba6 (patch)
tree0ed8d37d25744466786fa57c7fc22edb5c7c59d8 /src/soc
parente29dcdcdd8bc04e9c54aca4e341d0b8168763000 (diff)
soc/nvidia/tegra210: Fix flushing SPI fifo
This will avoid clearing the other bits in fifo_status. Change-Id: I7917b3f8d9af6056ed872b7e48cef9c3deba5119 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/nvidia/tegra210/spi.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c
index 0f38df2e6a..e6f667ac71 100644
--- a/src/soc/nvidia/tegra210/spi.c
+++ b/src/soc/nvidia/tegra210/spi.c
@@ -331,7 +331,7 @@ static void flush_fifos(struct tegra_spi_channel *spi)
uint32_t fifo_status = read32(&spi->regs->fifo_status);
fifo_status |= flush_mask;
- write32(&spi->regs->fifo_status, flush_mask);
+ write32(&spi->regs->fifo_status, fifo_status);
while (read32(&spi->regs->fifo_status) & flush_mask)
;