diff options
| author | Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com> | 2022-04-21 12:20:44 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-06 01:43:03 +0000 |
| commit | 7195cee17f0c2ac74806ae3a1005333c26f126e5 (patch) | |
| tree | 04684e913d4c4c92b2784e02b7c704e243ad80a4 /src/soc | |
| parent | 0a87c10f969d470f49db4d9558a4204b82d4a93a (diff) | |
soc/intel/alderlake: Add check for CSE FW sync in romstage
Some Alder Lake-N boards will use compressed ME RW blobs to obtain
savings on the SPI size (1916KB before compression, ~1132KB after
compression). So add an additional check before calling
cse_fw_sync() from romstage. When compressed blobs are used, the call to
CSE firmware update has to be in post-RAM stages.
BRANCH=firmware-brya-14505.B
Change-Id: I0d9ede52cb493974e4ba6e2e2cf11c9789b3b087
Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63760
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/alderlake/romstage/romstage.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index 31e629ccb5..f133910197 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -140,7 +140,7 @@ void mainboard_romstage_entry(void) s3wake = pmc_fill_power_state(ps) == ACPI_S3; - if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && !s3wake) { + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) { timestamp_add_now(TS_CSE_FW_SYNC_START); cse_fw_sync(); timestamp_add_now(TS_CSE_FW_SYNC_END); |