diff options
| author | Jes Klinke <jbk@google.com> | 2020-08-10 13:30:40 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-17 07:11:19 +0000 |
| commit | 6fd87ffe2e44ea8782446e00ac06f66612e32bec (patch) | |
| tree | cea45aa9d80775241acd63c15bca51fc7bebb09f /src/soc | |
| parent | 1df3b70c6a2eeb922bae96991f0a93e43e7e9721 (diff) | |
soc/intel/tigerlake: Allow fine grained control of S0iX states
Expose devicetree parameter to enable/disable each individual substate.
See https://review.coreboot.org/c/coreboot/+/43741 for context.
TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x
BUG=b:154333137
Change-Id: I8a0cf820e20961486813067c6945fe07bc4899f7
Signed-off-by: jbk@chromium.org
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44355
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 17 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 8 |
2 files changed, 25 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index dc910ff4c0..2da63ed21d 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -56,6 +56,20 @@ enum fivr_voltage_supported { #define FIVR_ENABLE_ALL_SX (FIVR_ENABLE_S0i1_S0i2 | FIVR_ENABLE_S0i3 | \ FIVR_ENABLE_S3 | FIVR_ENABLE_S4 | FIVR_ENABLE_S5) +/* Bit values for use in LpmStateEnableMask. */ +enum lpm_state_mask { + LPM_S0i2_0 = BIT(0), + LPM_S0i2_1 = BIT(1), + LPM_S0i2_2 = BIT(2), + LPM_S0i3_0 = BIT(3), + LPM_S0i3_1 = BIT(4), + LPM_S0i3_2 = BIT(5), + LPM_S0i3_3 = BIT(6), + LPM_S0i3_4 = BIT(7), + LPM_S0iX_ALL = LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2 + | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4, +}; + struct soc_intel_tigerlake_config { /* Common struct containing soc config data required by common code */ @@ -78,6 +92,9 @@ struct soc_intel_tigerlake_config { /* Enable S0iX support */ int s0ix_enable; + /* S0iX: Selectively disable individual sub-states, by default all are enabled. */ + enum lpm_state_mask LpmStateDisableMask; + /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */ uint8_t TcssD3HotDisable; /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */ diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index a61a0255bc..0a5fbe71e0 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -204,6 +204,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) sizeof(params->SataPortsDevSlp)); } + /* S0iX: Selectively enable individual sub-states, + * by default all are enabled. + * + * LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0, + * LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4 + */ + params->LpmStateEnableMask = LPM_S0iX_ALL & ~config->LpmStateDisableMask; + /* * Power Optimizer for DMI and SATA. * DmiPwrOptimizeDisable and SataPwrOptimizeDisable is default to 0. |