diff options
| author | Robert Zieba <robertzieba@google.com> | 2022-09-19 10:26:51 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-09 19:41:33 +0000 |
| commit | 6998ee069a33ab56307c43a4108276a020fc713f (patch) | |
| tree | 8e88a8bb8fda6d1e51cebf20b29a25096a7935eb /src/soc | |
| parent | 3db7b46804fd69cd7443e4c007248c4acff9f97a (diff) | |
soc/amd/cezanne: Set up SoC-specific XHCI definitions
Set up SoC-specific XHCI defines and enable SOC_AMD_COMMON_BLOCK_XHCI.
BRANCH=guybrush
BUG=b:186792595
TEST=builds
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I15e9c06cd38ac858b861a4d19626664704af7541
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67939
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/cezanne/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/xhci.h | 17 |
2 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 170bc49e39..046fd233f4 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -70,6 +70,7 @@ config SOC_AMD_CEZANNE select SOC_AMD_COMMON_FSP_DMI_TABLES select SOC_AMD_COMMON_FSP_PCI select SOC_AMD_COMMON_FSP_PRELOAD_FSPS + select SOC_AMD_COMMON_BLOCK_XHCI select SSE2 select UDK_2017_BINDING select USE_DDR4 diff --git a/src/soc/amd/cezanne/include/soc/xhci.h b/src/soc/amd/cezanne/include/soc/xhci.h new file mode 100644 index 0000000000..c590195731 --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/xhci.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_CEZANNE_XHCI_H +#define AMD_CEZANNE_XHCI_H + +#include <device/device.h> + +#define SOC_XHCI_0 DEV_PTR(xhci_0) +#define SOC_XHCI_1 DEV_PTR(xhci_1) +#define SOC_XHCI_2 NULL +#define SOC_XHCI_3 NULL +#define SOC_XHCI_4 NULL +#define SOC_XHCI_5 NULL +#define SOC_XHCI_6 NULL +#define SOC_XHCI_7 NULL + +#endif /* AMD_CEZANNE_XHCI_H */ |