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authorTim Wawrzynczak <twawrzynczak@chromium.org>2021-06-29 11:32:38 -0600
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-06-29 21:53:34 +0000
commit664c58ab95ff201bc986f96507de021d772bef74 (patch)
treef4de87cb67962b231b08d1922c68cf1d92344d92 /src/soc
parent61005c8eb53bec186bfa8a23e4f9ce755eed7437 (diff)
soc/intel/cannonlake: Add some missing DEVFN macros
BUG=b:130217151 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: If535ad0bdd46d3315493155e64968d305aa34799 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55967 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/cannonlake/include/soc/pci_devs.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h
index c9c51ca87e..a92b478a79 100644
--- a/src/soc/intel/cannonlake/include/soc/pci_devs.h
+++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h
@@ -22,6 +22,14 @@
#define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0)
#endif
+#define SA_DEV_SLOT_PEG 0x01
+#define SA_DEVFN_PEG0 PCI_DEVFN(SA_DEV_SLOT_PEG, 0)
+#define SA_DEVFN_PEG1 PCI_DEVFN(SA_DEV_SLOT_PEG, 1)
+#define SA_DEVFN_PEG2 PCI_DEVFN(SA_DEV_SLOT_PEG, 2)
+#define SA_DEV_PEG0 PCI_DEV(0, SA_DEV_SLOT_PEG, 0)
+#define SA_DEV_PEG1 PCI_DEV(0, SA_DEV_SLOT_PEG, 1)
+#define SA_DEV_PEG2 PCI_DEV(0, SA_DEV_SLOT_PEG, 2)
+
#define SA_DEV_SLOT_IGD 0x02
#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0)
#define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0)
@@ -34,6 +42,10 @@
#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0)
#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0)
+#define SA_DEV_SLOT_GNA 0x08
+#define SA_DEVFN_GNA PCI_DEVFN(SA_DEV_SLOT_GNA, 0)
+#define SA_DEV_GNA PCI_DEV(0, SA_DEV_SLOT_GNA, 0)
+
/* PCH Devices */
#define PCH_DEV_SLOT_THERMAL 0x12
#define PCH_DEVFN_THERMAL _PCH_DEVFN(THERMAL, 0)