diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-12-08 00:12:06 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-12-09 14:42:27 +0000 |
| commit | 5af890d666755ee8e21d605e3564a3dfa5f6796d (patch) | |
| tree | e5403d1e29bbb90198f2aba20ef70bfe86f18fb6 /src/soc | |
| parent | 2a8de6dafb7eec8ff9112b43888507fbc0d8f851 (diff) | |
soc/amd/common/block/psp: add psp_efs.c to build for both PSP GEN1&2
The PSP EFS code to get the SPI mode and speed from the amdfw part of
the firmware image also works for Stoneyridge which is the one SoC that
selects SOC_AMD_COMMON_BLOCK_PSP_GEN1. Also amdblocks/psp_efs.h already
handles the SOC_AMD_STONEYRIDGE case.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibddd3f9237e561d9f0f6b4ad70f59cce1f956986
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/common/block/psp/Makefile.inc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/amd/common/block/psp/Makefile.inc b/src/soc/amd/common/block/psp/Makefile.inc index 2b407a2b4c..94dc57ca8f 100644 --- a/src/soc/amd/common/block/psp/Makefile.inc +++ b/src/soc/amd/common/block/psp/Makefile.inc @@ -5,6 +5,9 @@ ramstage-y += psp.c smm-y += psp.c smm-y += psp_smm.c +bootblock-y += psp_efs.c +verstage-y += psp_efs.c + endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1),y) @@ -22,7 +25,4 @@ ramstage-y += psp_gen2.c smm-y += psp_gen2.c smm-y += psp_smm_gen2.c -bootblock-y += psp_efs.c -verstage-y += psp_efs.c - endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2 |