diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2024-01-09 16:59:37 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-01-11 14:42:03 +0000 |
| commit | 5913a54a3be35f4dc8e66878de443fd4c906899b (patch) | |
| tree | a6e0538937e642bc9b887d619fdd91add4f7d3bf /src/soc | |
| parent | ba48ca8e4a6ad2ca6ffedd393b298cb89ed5560e (diff) | |
soc/amd/stoneyridge/northbridge: report GNB IOAPIC in domain
Move the GNB IOAPIC resource from being reported in the GNB PCI device
to the domain and use IOMMU_IOAPIC_IDX as resource index, so that the
common AMD MADT code will be able to find the resource.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If6e9aaf4a3fa2c5b0266fd9fb8254285f8555317
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/stoneyridge/northbridge.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index bf2f992e33..2b6ba45bff 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -43,9 +43,6 @@ static void read_resources(struct device *dev) * the CPU_CLUSTER. */ mmconf_resource(dev, idx++); - - /* NB IOAPIC2 resource */ - mmio_range(dev, idx++, IO_APIC2_ADDR, 0x1000); } /** @@ -301,6 +298,10 @@ void domain_read_resources(struct device *dev) /* Low top usable RAM -> Low top RAM (bottom pci mmio hole) */ reserved_ram_from_to(dev, idx++, mem_useable, tom); + /* NB IOAPIC2 resource. IOMMU_IOAPIC_IDX is used as index, so that the common AMD MADT + code can find this resource */ + mmio_range(dev, IOMMU_IOAPIC_IDX, IO_APIC2_ADDR, 0x1000); + /* If there is memory above 4GiB */ if (high_tom >> 32) { /* 4GiB -> high top usable */ |