diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-05-19 11:31:10 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-09-15 14:47:52 +0000 |
| commit | 56776a1ab39333c791903e0a7e79e8fb51d3162d (patch) | |
| tree | ffce5f6c84b0643cf6eaf0b288d2566d30796064 /src/soc | |
| parent | 576861994ea5011c3a836a826b8189ef79c366cb (diff) | |
soc/amd: Do SMM relocation via MSR
AMD CPUs have a convenient MSR that allows to set the SMBASE in the save
state without ever entering SMM (e.g. at the default 0x30000 address).
This has been a feature in all AMD CPUs since at least AMD K8. This
allows to do relocation in parallel in ramstage and without setting up a
relocation handler, which likely results in a speedup. The more cores
the higher the speedup as relocation was happening sequentially. On a 4
core AMD picasso system this results in 33ms boot speedup.
TESTED on google/vilboz (Picasso) with CONFIG_SMI_DEBUG: verify that SMM
is correctly relocated with the BSP correctly entering the smihandler.
Change-Id: I9729fb94ed5c18cfd57b8098c838c08a04490e4b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/common/block/cpu/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/amd/common/block/cpu/smm/smm_relocate.c | 14 |
2 files changed, 9 insertions, 6 deletions
diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index 0665e7d6f9..cdd5c3a69e 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -57,6 +57,7 @@ config SOC_AMD_COMMON_BLOCK_MCAX config SOC_AMD_COMMON_BLOCK_SMM bool + select X86_SMM_SKIP_RELOCATION_HANDLER if HAVE_SMI_HANDLER help Add common SMM relocation, finalization and handler functionality to the build. diff --git a/src/soc/amd/common/block/cpu/smm/smm_relocate.c b/src/soc/amd/common/block/cpu/smm/smm_relocate.c index 87636df850..4d33b65314 100644 --- a/src/soc/amd/common/block/cpu/smm/smm_relocate.c +++ b/src/soc/amd/common/block/cpu/smm/smm_relocate.c @@ -57,10 +57,8 @@ static void tseg_valid(void) wrmsr(SMM_MASK_MSR, mask); } -static void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase) +static void smm_relocation_handler(void) { - amd64_smm_state_save_area_t *smm_state; - uintptr_t tseg_base; size_t tseg_size; @@ -76,8 +74,12 @@ static void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t sta msr.hi = (1 << (cpu_phys_address_size() - 32)) - 1; wrmsr(SMM_MASK_MSR, msr); - smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase); - smm_state->smbase = staggered_smbase; + uintptr_t smbase = smm_get_cpu_smbase(cpu_index()); + msr_t smm_base = { + .hi = 0, + .lo = smbase + }; + wrmsr(SMM_BASE_MSR, smm_base); tseg_valid(); lock_smm(); @@ -87,6 +89,6 @@ const struct mp_ops amd_mp_ops_with_smm = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, .get_smm_info = get_smm_info, - .relocation_handler = smm_relocation_handler, + .per_cpu_smm_trigger = smm_relocation_handler, .post_mp_init = global_smi_enable, }; |