soc/intel/skylake: Refactor pch_early_init() code

This patch keeps required pch_early_init() function like ABASE programming,
GPE and RTC init into bootblock and moves remaining functions like
TCO configuration and SMBUS init into romstage/pch.c in order to maintain
only required chipset programming for bootblock and verstage.

TEST=Able to build and boot soraka.

Change-Id: Idf7b04edc3fce147f7857591ce7d5a0cd03f43fe
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

7 files changed, 35 insertions, 16 deletions

diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c
index 596e3f184f..d1fbb83b8a 100644
--- a/src/soc/intel/skylake/bootblock/bootblock.c
+++ b/src/soc/intel/skylake/bootblock/bootblock.c
@@ -44,7 +44,6 @@ void bootblock_soc_init(void)
 	 * and abase, i2c programming and print platform info
 	 */
 	report_platform_info();
-	pch_early_init();
-
+	pch_init();
 	gspi_early_bar_init();
 }
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index c95a8d80e8..332060ed2d 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015-2018 Intel Corporation.
+ * Copyright (C) 2015-2019 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -24,8 +24,6 @@
 #include <intelblocks/pcr.h>
 #include <intelblocks/pmclib.h>
 #include <intelblocks/rtc.h>
-#include <intelblocks/smbus.h>
-#include <intelblocks/tco.h>
 #include <soc/bootblock.h>
 #include <soc/iomap.h>
 #include <soc/p2sb.h>
@@ -34,8 +32,6 @@
 #include <soc/pcr_ids.h>
 #include <soc/pm.h>
 #include <soc/pmc.h>
-#include <soc/smbus.h>
-
 #include "../chip.h"
 
 #define PCR_DMI_DMICTL		0x2234
@@ -150,7 +146,7 @@ void pch_early_iorange_init(void)
 	pch_enable_lpc();
 }
 
-void pch_early_init(void)
+void pch_init(void)
 {
 	/*
 	 * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
@@ -164,12 +160,6 @@ void pch_early_init(void)
 	 */
 	soc_config_pwrmbase();
 
-	/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
-	tco_configure();
-
-	/* Program SMBUS_BASE_ADDRESS and Enable it */
-	smbus_common_init();
-
 	/* Set up GPE configuration */
 	pmc_gpe_init();
 
diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h
index a40f439936..302db50fb3 100644
--- a/src/soc/intel/skylake/include/soc/bootblock.h
+++ b/src/soc/intel/skylake/include/soc/bootblock.h
@@ -24,7 +24,7 @@ void bootblock_pch_early_init(void);
 
 /* Bootblock post console init programming */
 void i2c_early_init(void);
-void pch_early_init(void);
+void pch_init(void);
 void pch_early_iorange_init(void);
 void report_platform_info(void);
 void report_memory_config(void);
diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h
index 364bf52529..674652625b 100644
--- a/src/soc/intel/skylake/include/soc/romstage.h
+++ b/src/soc/intel/skylake/include/soc/romstage.h
@@ -21,6 +21,7 @@
 
 void mainboard_memory_init_params(FSPM_UPD *mupd);
 void systemagent_early_init(void);
+void pch_init(void);
 int smbus_read_byte(unsigned int device, unsigned int address);
 /* Board type */
 enum board_type {
diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc
index dff89ce2dc..1b069b6d49 100644
--- a/src/soc/intel/skylake/romstage/Makefile.inc
+++ b/src/soc/intel/skylake/romstage/Makefile.inc
@@ -1,3 +1,4 @@
 romstage-y += ../../../../cpu/intel/car/romstage.c
 romstage-y += romstage.c
 romstage-y += systemagent.c
+romstage-y += pch.c
diff --git a/src/soc/intel/skylake/romstage/pch.c b/src/soc/intel/skylake/romstage/pch.c
new file mode 100644
index 0000000000..88a7cc7163
--- /dev/null
+++ b/src/soc/intel/skylake/romstage/pch.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <intelblocks/smbus.h>
+#include <intelblocks/tco.h>
+#include <soc/romstage.h>
+
+void pch_init(void)
+{
+	/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
+	tco_configure();
+
+	/* Program SMBUS_BASE_ADDRESS and Enable it */
+	smbus_common_init();
+}
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index a72b261a56..2904f05f01 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -146,7 +146,8 @@ void mainboard_romstage_entry(void)
 
 	/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
 	systemagent_early_init();
-
+	/* Program PCH init */
+	pch_init();
 	ps = pmc_get_power_state();
 	s3wake = pmc_fill_power_state(ps) == ACPI_S3;
 	fsp_memory_init(s3wake);