soc/intel/fsp_baytrail: Get rid of device_t

Use of device_t has been abandoned in ramstage.

Change-Id: I52534b67cd3cd8489925941f45a756b3d430e072
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

13 files changed, 50 insertions, 50 deletions

diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c
index 015681652e..7ce1b35d42 100644
--- a/src/soc/intel/fsp_baytrail/acpi.c
+++ b/src/soc/intel/fsp_baytrail/acpi.c
@@ -499,7 +499,7 @@ static void generate_P_state_entries(int core, int cores_per_package)
 	acpigen_pop_len();
 }
 
-void generate_cpu_entries(device_t device)
+void generate_cpu_entries(struct device *device)
 {
 	int core;
 	int pcontrol_blk = get_pmbase(), plen = 6;
@@ -553,7 +553,7 @@ unsigned long acpi_madt_irq_overrides(unsigned long current)
 	return current;
 }
 
-unsigned long southcluster_write_acpi_tables(device_t device,
+unsigned long southcluster_write_acpi_tables(struct device *device,
 					     unsigned long current,
 					     struct acpi_rsdp *rsdp)
 {
@@ -581,7 +581,7 @@ unsigned long southcluster_write_acpi_tables(device_t device,
 	return current;
 }
 
-void southcluster_inject_dsdt(device_t device)
+void southcluster_inject_dsdt(struct device *device)
 {
 	global_nvs_t *gnvs;
 
diff --git a/src/soc/intel/fsp_baytrail/chip.c b/src/soc/intel/fsp_baytrail/chip.c
index 814417aa37..a041b81da6 100644
--- a/src/soc/intel/fsp_baytrail/chip.c
+++ b/src/soc/intel/fsp_baytrail/chip.c
@@ -21,7 +21,7 @@
 #include <drivers/intel/fsp1_0/fsp_util.h>
 #include "chip.h"
 
-static void pci_domain_set_resources(device_t dev)
+static void pci_domain_set_resources(struct device *dev)
 {
 	assign_resources(dev->link_list);
 }
@@ -42,7 +42,7 @@ static struct device_operations cpu_bus_ops = {
 	.scan_bus         = NULL,
 };
 
-static void enable_dev(device_t dev)
+static void enable_dev(struct device *dev)
 {
 	printk(BIOS_DEBUG, "enable_dev(%s, %d)\n",
 	       dev_name(dev), dev->path.type);
@@ -73,7 +73,7 @@ struct chip_operations soc_intel_fsp_baytrail_ops = {
 	.init = soc_init,
 };
 
-static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
 {
 	if (!vendor || !device) {
 		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c
index 38c4446e01..c7694b9824 100644
--- a/src/soc/intel/fsp_baytrail/cpu.c
+++ b/src/soc/intel/fsp_baytrail/cpu.c
@@ -42,7 +42,7 @@ static const struct reg_script core_msr_script[] = {
 	REG_SCRIPT_END
 };
 
-static void baytrail_core_init(device_t cpu)
+static void baytrail_core_init(struct device *cpu)
 {
 	printk(BIOS_DEBUG, "Init BayTrail core.\n");
 
@@ -164,7 +164,7 @@ static const struct mp_ops mp_ops = {
 	.post_mp_init = enable_smis,
 };
 
-void baytrail_init_cpus(device_t dev)
+void baytrail_init_cpus(struct device *dev)
 {
 	struct bus *cpu_bus = dev->link_list;
 
diff --git a/src/soc/intel/fsp_baytrail/gfx.c b/src/soc/intel/fsp_baytrail/gfx.c
index 62224fa850..5464b66bf8 100644
--- a/src/soc/intel/fsp_baytrail/gfx.c
+++ b/src/soc/intel/fsp_baytrail/gfx.c
@@ -74,24 +74,24 @@ static const struct reg_script gfx_post_vbios_script[] = {
 	REG_SCRIPT_END
 };
 
-static inline void gfx_run_script(device_t dev, const struct reg_script *ops)
+static inline void gfx_run_script(struct device *dev, const struct reg_script *ops)
 {
 	reg_script_run_on_dev(dev, ops);
 }
 
-static void gfx_pre_vbios_init(device_t dev)
+static void gfx_pre_vbios_init(struct device *dev)
 {
 	printk(BIOS_INFO, "GFX: Pre VBIOS Init\n");
 	gfx_run_script(dev, gpu_pre_vbios_script);
 }
 
-static void gfx_post_vbios_init(device_t dev)
+static void gfx_post_vbios_init(struct device *dev)
 {
 	printk(BIOS_INFO, "GFX: Post VBIOS Init\n");
 	gfx_run_script(dev, gfx_post_vbios_script);
 }
 
-static void gfx_init(device_t dev)
+static void gfx_init(struct device *dev)
 {
 	/* Pre VBIOS Init */
 	gfx_pre_vbios_init(dev);
diff --git a/src/soc/intel/fsp_baytrail/i2c.c b/src/soc/intel/fsp_baytrail/i2c.c
index 4565ba4ced..95761f3d19 100644
--- a/src/soc/intel/fsp_baytrail/i2c.c
+++ b/src/soc/intel/fsp_baytrail/i2c.c
@@ -100,7 +100,7 @@ static int wait_for_idle(char *base_adr)
  */
 int i2c_init(unsigned bus)
 {
-	device_t dev;
+	struct device *dev;
 	int base_adr[7] = {I2C0_MEM_BASE, I2C1_MEM_BASE, I2C2_MEM_BASE,
 			   I2C3_MEM_BASE, I2C4_MEM_BASE, I2C5_MEM_BASE,
 			   I2C6_MEM_BASE};
@@ -166,7 +166,7 @@ int i2c_read(unsigned bus, unsigned chip, unsigned addr,
 {
 	int i = 0;
 	char *base_ptr = NULL;
-	device_t dev;
+	struct device *dev;
 	unsigned int val;
 	int stat;
 
@@ -225,7 +225,7 @@ int i2c_write(unsigned bus, unsigned chip, unsigned addr,
 {
 	int i;
 	char *base_ptr;
-	device_t dev;
+	struct device *dev;
 	unsigned int val;
 	int stat;
 
diff --git a/src/soc/intel/fsp_baytrail/include/soc/acpi.h b/src/soc/intel/fsp_baytrail/include/soc/acpi.h
index 388ebc29ed..27b700096f 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/acpi.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/acpi.h
@@ -28,10 +28,10 @@ unsigned long acpi_madt_irq_overrides(unsigned long current);
 void acpi_init_gnvs(global_nvs_t *gnvs);
 
 #ifndef __SIMPLE_DEVICE__
-unsigned long southcluster_write_acpi_tables(device_t device,
+unsigned long southcluster_write_acpi_tables(struct device *device,
 					     unsigned long current,
 					     struct acpi_rsdp *rsdp);
-void southcluster_inject_dsdt(device_t device);
+void southcluster_inject_dsdt(struct device *device);
 #endif
 
 #endif /* _BAYTRAIL_ACPI_H_ */
diff --git a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h
index bc75567ce0..82fd0a1c2f 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h
@@ -56,7 +56,7 @@ void rangeley_early_initialization(void);
 int soc_silicon_revision(void);
 int soc_silicon_type(void);
 int soc_silicon_supported(int type, int rev);
-void soc_enable(device_t dev);
+void soc_enable(struct device *dev);
 
 /* debugging functions */
 void print_pci_devices(void);
diff --git a/src/soc/intel/fsp_baytrail/include/soc/ramstage.h b/src/soc/intel/fsp_baytrail/include/soc/ramstage.h
index 5c2f98aa11..e8f81bb5c0 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/ramstage.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/ramstage.h
@@ -21,10 +21,10 @@
 /* The baytrail_init_pre_device() function is called prior to device
  * initialization, but it's after console and cbmem has been reinitialized. */
 void baytrail_init_pre_device(void);
-void baytrail_init_cpus(device_t dev);
+void baytrail_init_cpus(struct device *dev);
 void set_max_freq(void);
-void southcluster_enable_dev(device_t dev);
-void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index);
+void southcluster_enable_dev(struct device *dev);
+void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index);
 
 extern struct pci_operations soc_pci_ops;
 
diff --git a/src/soc/intel/fsp_baytrail/lpe.c b/src/soc/intel/fsp_baytrail/lpe.c
index 4fbdce15a4..84a10fd9cd 100644
--- a/src/soc/intel/fsp_baytrail/lpe.c
+++ b/src/soc/intel/fsp_baytrail/lpe.c
@@ -41,7 +41,7 @@
 #define FIRMWARE_REG_BASE_C0 0x144000
 #define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4)
 
-static void assign_device_nvs(device_t dev, u32 *field, unsigned index)
+static void assign_device_nvs(struct device *dev, u32 *field, unsigned index)
 {
 	struct resource *res;
 
@@ -50,7 +50,7 @@ static void assign_device_nvs(device_t dev, u32 *field, unsigned index)
 		*field = res->base;
 }
 
-static void lpe_enable_acpi_mode(device_t dev)
+static void lpe_enable_acpi_mode(struct device *dev)
 {
 	static const struct reg_script ops[] = {
 		/* Disable PCI interrupt, enable Memory and Bus Master */
@@ -83,7 +83,7 @@ static void lpe_enable_acpi_mode(device_t dev)
 	reg_script_run_on_dev(dev, ops);
 }
 
-static void setup_codec_clock(device_t dev)
+static void setup_codec_clock(struct device *dev)
 {
 	uint32_t reg;
 	u32 *clk_reg;
@@ -121,7 +121,7 @@ static void setup_codec_clock(device_t dev)
 	write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);
 }
 
-static void lpe_stash_firmware_info(device_t dev)
+static void lpe_stash_firmware_info(struct device *dev)
 {
 	struct resource *res;
 	struct resource *mmio;
@@ -147,7 +147,7 @@ static void lpe_stash_firmware_info(device_t dev)
 	}
 }
 
-static void lpe_init(device_t dev)
+static void lpe_init(struct device *dev)
 {
 	struct soc_intel_fsp_baytrail_config *config = dev->chip_info;
 
@@ -159,7 +159,7 @@ static void lpe_init(device_t dev)
 		lpe_enable_acpi_mode(dev);
 }
 
-static void lpe_read_resources(device_t dev)
+static void lpe_read_resources(struct device *dev)
 {
 	pci_dev_read_resources(dev);
 
diff --git a/src/soc/intel/fsp_baytrail/lpss.c b/src/soc/intel/fsp_baytrail/lpss.c
index 427fc6da1c..8820eed30f 100644
--- a/src/soc/intel/fsp_baytrail/lpss.c
+++ b/src/soc/intel/fsp_baytrail/lpss.c
@@ -29,7 +29,7 @@
 
 #include "chip.h"
 
-static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index)
+static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
 {
 	struct reg_script ops[] = {
 		/* Disable PCI interrupt, enable Memory and Bus Master */
@@ -66,7 +66,7 @@ static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index)
 	reg_script_run_on_dev(dev, ops);
 }
 
-static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg)
+static void dev_enable_snoop_and_pm(struct device *dev, int iosf_reg)
 {
 	struct reg_script ops[] = {
 		REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg,
@@ -78,7 +78,7 @@ static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg)
 	reg_script_run_on_dev(dev, ops);
 }
 
-static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index)
+static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index)
 {
 	*iosf_reg = -1;
 	*nvs_index = -1;
@@ -119,7 +119,7 @@ static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index)
 	}
 }
 
-static void i2c_disable_resets(device_t dev)
+static void i2c_disable_resets(struct device *dev)
 {
 	/* Release the I2C devices from reset. */
 	static const struct reg_script ops[] = {
@@ -146,7 +146,7 @@ static void i2c_disable_resets(device_t dev)
 	}
 }
 
-static void lpss_init(device_t dev)
+static void lpss_init(struct device *dev)
 {
 	struct soc_intel_fsp_baytrail_config *config = dev->chip_info;
 	int iosf_reg, nvs_index;
diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c
index b4aceeeba7..9f22b25a5d 100644
--- a/src/soc/intel/fsp_baytrail/northcluster.c
+++ b/src/soc/intel/fsp_baytrail/northcluster.c
@@ -88,7 +88,7 @@ uint32_t nc_read_top_of_low_memory(void)
 
 static int get_pcie_bar(u32 *base)
 {
-	device_t dev;
+	struct device *dev;
 	u32 pciexbar_reg;
 
 	*base = 0;
@@ -123,7 +123,7 @@ static int add_fixed_resources(struct device *dev, int index)
 	return index;
 }
 
-static void mc_add_dram_resources(device_t dev)
+static void mc_add_dram_resources(struct device *dev)
 {
 	u32 bmbound, bsmmrrl;
 	int index = 0;
@@ -166,7 +166,7 @@ static void mc_add_dram_resources(device_t dev)
 	index = add_fixed_resources(dev, index);
 }
 
-static void nc_read_resources(device_t dev)
+static void nc_read_resources(struct device *dev)
 {
 	u32 pcie_config_base;
 	int buses;
@@ -185,7 +185,7 @@ static void nc_read_resources(device_t dev)
 	mc_add_dram_resources(dev);
 }
 
-static void nc_enable(device_t dev)
+static void nc_enable(struct device *dev)
 {
 	print_fsp_info();
 }
diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c
index a322ee351e..fc50e649bf 100644
--- a/src/soc/intel/fsp_baytrail/ramstage.c
+++ b/src/soc/intel/fsp_baytrail/ramstage.c
@@ -73,7 +73,7 @@ static const char *stepping_str[] = {
 
 static void fill_in_pattrs(void)
 {
-	device_t dev;
+	struct device *dev;
 	msr_t msr;
 	struct pattrs *attrs = (struct pattrs *)pattrs_get();
 
diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c
index a547152b5c..6fa2192c52 100644
--- a/src/soc/intel/fsp_baytrail/southcluster.c
+++ b/src/soc/intel/fsp_baytrail/southcluster.c
@@ -50,12 +50,12 @@
 typedef struct soc_intel_fsp_baytrail_config config_t;
 
 static inline void
-add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size)
+add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size)
 {
 	mmio_resource(dev, i, addr >> 10, size >> 10);
 }
 
-static void sc_add_mmio_resources(device_t dev)
+static void sc_add_mmio_resources(struct device *dev)
 {
 	add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE);
 	add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE);
@@ -167,8 +167,8 @@ static void sc_enable_serial_irqs(struct device *dev)
  */
 static void write_pci_config_irqs(void)
 {
-	device_t irq_dev;
-	device_t targ_dev;
+	struct device *irq_dev;
+	struct device *targ_dev;
 	uint8_t int_line = 0;
 	uint8_t original_int_pin = 0;
 	uint8_t new_int_pin = 0;
@@ -261,7 +261,7 @@ static void write_pci_config_irqs(void)
 	printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n");
 }
 
-static void sc_pirq_init(device_t dev)
+static void sc_pirq_init(struct device *dev)
 {
 	int i, j;
 	int pirq;
@@ -324,7 +324,7 @@ static inline int io_range_in_default(int base, int size)
  * Note: this function assumes there is no overlap with the default LPC device's
  * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
  */
-static void sc_add_io_resource(device_t dev, int base, int size, int index)
+static void sc_add_io_resource(struct device *dev, int base, int size, int index)
 {
 	struct resource *res;
 
@@ -338,7 +338,7 @@ static void sc_add_io_resource(device_t dev, int base, int size, int index)
 	             IORESOURCE_FIXED;
 }
 
-static void sc_add_io_resources(device_t dev)
+static void sc_add_io_resources(struct device *dev)
 {
 	struct resource *res;
 	u8 io_index = 0;
@@ -360,7 +360,7 @@ static void sc_add_io_resources(device_t dev)
 	sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE);
 }
 
-static void sc_read_resources(device_t dev)
+static void sc_read_resources(struct device *dev)
 {
 	/* Get the normal PCI resources of this device. */
 	pci_dev_read_resources(dev);
@@ -415,7 +415,7 @@ static void sc_init(struct device *dev)
  */
 
 /* Set bit in function disable register to hide this device. */
-static void sc_disable_devfn(device_t dev)
+static void sc_disable_devfn(struct device *dev)
 {
 	u32 *func_dis = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS);
 	u32 *func_dis2 = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS2);
@@ -463,7 +463,7 @@ static void sc_disable_devfn(device_t dev)
 	}
 }
 
-static inline void set_d3hot_bits(device_t dev, int offset)
+static inline void set_d3hot_bits(struct device *dev, int offset)
 {
 	uint32_t reg8;
 	printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset);
@@ -475,7 +475,7 @@ static inline void set_d3hot_bits(device_t dev, int offset)
 /* Parts of the audio subsystem are powered by the HDA device. Therefore, one
  * cannot put HDA into D3Hot. Instead perform this workaround to make some of
  * the audio paths work for LPE audio. */
-static void hda_work_around(device_t dev)
+static void hda_work_around(struct device *dev)
 {
 	u32 *gctl = (u32 *)(TEMP_BASE_ADDRESS + 0x8);
 
@@ -492,7 +492,7 @@ static void hda_work_around(device_t dev)
 	pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0);
 }
 
-static int place_device_in_d3hot(device_t dev)
+static int place_device_in_d3hot(struct device *dev)
 {
 	unsigned offset;
 
@@ -569,7 +569,7 @@ static int place_device_in_d3hot(device_t dev)
 }
 
 /* Common PCI device function disable. */
-void southcluster_enable_dev(device_t dev)
+void southcluster_enable_dev(struct device *dev)
 {
 	uint32_t reg32;