Rename ECAM-specific MMCONF Kconfigs

Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space.  Some platforms have a different way of mapping the PCI config
space to memory.  This patch renames the following configs to
make it clear that these configs are ECAM-specific:

- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH

Please refer to CB:57861 "Proposed coreboot Changes" for more
details.

BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
     Make sure Jenkins verifies that builds on other boards

Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

40 files changed, 66 insertions, 66 deletions

diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index dbafa8c11d..16f1d3fdcd 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -216,10 +216,10 @@ config RO_REGION_ONLY
 	depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A
 	default "apu/amdfw"
 
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
 	default 0xF8000000
 
-config MMCONF_BUS_NUMBER
+config ECAM_MMCONF_BUS_NUMBER
 	default 64
 
 config MAX_CPUS
diff --git a/src/soc/amd/cezanne/acpi/pci0.asl b/src/soc/amd/cezanne/acpi/pci0.asl
index f9956b68c5..08ccbe6cf0 100644
--- a/src/soc/amd/cezanne/acpi/pci0.asl
+++ b/src/soc/amd/cezanne/acpi/pci0.asl
@@ -66,14 +66,14 @@ Device(PCI0) {
 
 		/* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */
 		MM1B = TOM1
-		Local0 = CONFIG_MMCONF_BASE_ADDRESS
+		Local0 = CONFIG_ECAM_MMCONF_BASE_ADDRESS
 		Local0 -= TOM1
 		MM1L = Local0
 
 		CreateWordField(CRES, ^PSB0._MAX, BMAX)
 		CreateWordField(CRES, ^PSB0._LEN, BLEN)
-		BMAX = CONFIG_MMCONF_BUS_NUMBER - 1
-		BLEN = CONFIG_MMCONF_BUS_NUMBER
+		BMAX = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1
+		BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER
 
 		Return(CRES) /* note to change the Name buffer */
 	} /* end of Method(_SB.PCI0._CRS) */
diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c
index 9f594d96ac..048b428521 100644
--- a/src/soc/amd/cezanne/fsp_m_params.c
+++ b/src/soc/amd/cezanne/fsp_m_params.c
@@ -70,7 +70,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 
 	mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache();
 
-	mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS;
+	mcfg->pci_express_base_addr = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
 	mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE;
 	mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
 	mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM);
diff --git a/src/soc/amd/common/block/pci/amd_pci_mmconf.c b/src/soc/amd/common/block/pci/amd_pci_mmconf.c
index cb221e2289..fb4db39ac5 100644
--- a/src/soc/amd/common/block/pci/amd_pci_mmconf.c
+++ b/src/soc/amd/common/block/pci/amd_pci_mmconf.c
@@ -10,7 +10,7 @@ void enable_pci_mmconf(void)
 	msr_t mmconf;
 
 	mmconf.hi = 0;
-	mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN
-			| fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT;
+	mmconf.lo = CONFIG_ECAM_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN
+			| fms(CONFIG_ECAM_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT;
 	wrmsr(MMIO_CONF_BASE, mmconf);
 }
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 6fc482519b..92607a3530 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -200,10 +200,10 @@ config RAMBASE
 	hex
 	default 0x10000000
 
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
 	default 0xF8000000
 
-config MMCONF_BUS_NUMBER
+config ECAM_MMCONF_BUS_NUMBER
 	default 64
 
 config VERSTAGE_ADDR
diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
index 292cdd8318..df21e9d9a5 100644
--- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
+++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
@@ -73,14 +73,14 @@ Method(_CRS, 0) {
 
 	/* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */
 	MM1B = TOM1
-	Local0 = CONFIG_MMCONF_BASE_ADDRESS
+	Local0 = CONFIG_ECAM_MMCONF_BASE_ADDRESS
 	Local0 -= TOM1
 	MM1L = Local0
 
 	CreateWordField(CRES, ^PSB0._MAX, BMAX)
 	CreateWordField(CRES, ^PSB0._LEN, BLEN)
-	BMAX = CONFIG_MMCONF_BUS_NUMBER - 1
-	BLEN = CONFIG_MMCONF_BUS_NUMBER
+	BMAX = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1
+	BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER
 
 	Return(CRES) /* note to change the Name buffer */
 } /* end of Method(_SB.PCI0._CRS) */
diff --git a/src/soc/amd/picasso/fsp_m_params.c b/src/soc/amd/picasso/fsp_m_params.c
index 6a5c07425f..6483394294 100644
--- a/src/soc/amd/picasso/fsp_m_params.c
+++ b/src/soc/amd/picasso/fsp_m_params.c
@@ -19,7 +19,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 
 	mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache();
 
-	mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS;
+	mcfg->pci_express_base_addr = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
 	mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE;
 	mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
 	mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM);
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index ec36b34b7d..50e66b0a79 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -120,10 +120,10 @@ config BOTTOMIO_POSITION
 	  option is useful when PCI peripherals requesting large address
 	  ranges are present.
 
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
 	default 0xF8000000
 
-config MMCONF_BUS_NUMBER
+config ECAM_MMCONF_BUS_NUMBER
 	default 64
 
 config VGA_BIOS_ID
diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig
index 87edf45cde..368581f8f1 100644
--- a/src/soc/cavium/cn81xx/Kconfig
+++ b/src/soc/cavium/cn81xx/Kconfig
@@ -9,7 +9,7 @@ config SOC_CAVIUM_CN81XX
 	select UART_OVERRIDE_REFCLK
 	select SOC_CAVIUM_COMMON
 	select CAVIUM_BDK_DDR_TUNE_HW_OFFSETS
-	select MMCONF_SUPPORT
+	select ECAM_MMCONF_SUPPORT
 	select PCI
 
 if SOC_CAVIUM_CN81XX
@@ -36,7 +36,7 @@ config HEAP_SIZE
 config STACK_SIZE
 	default 0x2000
 
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
 	default 0x848000000000
 
 endif
diff --git a/src/soc/example/min86/Kconfig b/src/soc/example/min86/Kconfig
index 660bf369e7..d1767523dd 100644
--- a/src/soc/example/min86/Kconfig
+++ b/src/soc/example/min86/Kconfig
@@ -16,7 +16,7 @@ config SOC_SPECIFIC_OPTIONS
 	def_bool y
 	select ARCH_X86
 	select NO_MONOTONIC_TIMER
-	select NO_MMCONF_SUPPORT
+	select NO_ECAM_MMCONF_SUPPORT
 	select UNKNOWN_TSC_RATE
 
 config DCACHE_BSP_STACK_SIZE		# required by arch/x86/car.ld
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 214829afb0..58b9051e6d 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -203,7 +203,7 @@ config PCR_BASE_ADDRESS
 	help
 	  This option allows you to select MMIO Base Address of sideband bus.
 
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
 	default 0xc0000000
 
 config CPU_BCLK_MHZ
diff --git a/src/soc/intel/alderlake/systemagent.c b/src/soc/intel/alderlake/systemagent.c
index 6bd02ee02b..1736e32e71 100644
--- a/src/soc/intel/alderlake/systemagent.c
+++ b/src/soc/intel/alderlake/systemagent.c
@@ -25,7 +25,7 @@
 void soc_add_fixed_mmio_resources(struct device *dev, int *index)
 {
 	static const struct sa_mmio_descriptor soc_fixed_resources[] = {
-		{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH,
+		{ PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
 				"PCIEXBAR" },
 		{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
 		{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
diff --git a/src/soc/intel/apollolake/systemagent.c b/src/soc/intel/apollolake/systemagent.c
index b8f7995b75..d6e23acb59 100644
--- a/src/soc/intel/apollolake/systemagent.c
+++ b/src/soc/intel/apollolake/systemagent.c
@@ -18,7 +18,7 @@
 void soc_add_fixed_mmio_resources(struct device *dev, int *index)
 {
 	static const struct sa_mmio_descriptor soc_fixed_resources[] = {
-		{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH,
+		{ PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
 				"PCIEXBAR" },
 		{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
 	};
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 9f1cb8e820..c2d24b29c6 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -39,10 +39,10 @@ config VBOOT
 	select VBOOT_MUST_REQUEST_DISPLAY
 	select VBOOT_STARTS_IN_ROMSTAGE
 
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
 	default 0xe0000000
 
-config MMCONF_BUS_NUMBER
+config ECAM_MMCONF_BUS_NUMBER
 	int
 	default 256
 
diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl
index 5f20463c2a..c994fdabbe 100644
--- a/src/soc/intel/baytrail/acpi/southcluster.asl
+++ b/src/soc/intel/baytrail/acpi/southcluster.asl
@@ -144,7 +144,7 @@ Name (MCRS, ResourceTemplate()
 			0x00000000, 0x00000000, 0x00000000, 0x00000000,
 			0x00000000,,, LMEM)
 
-	/* PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) */
+	/* PCI Memory Region (Top of memory-CONFIG_ECAM_MMCONF_BASE_ADDRESS) */
 	DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 			Cacheable, ReadWrite,
 			0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -184,7 +184,7 @@ Method (_CRS, 0, Serialized)
 
 	/* TOLM is BMBOUND accessible from IOSF so is saved in NVS */
 	Store (\TOLM, PMIN)
-	Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX)
+	Store (Subtract(CONFIG_ECAM_MMCONF_BASE_ADDRESS, 1), PMAX)
 	Add (Subtract (PMAX, PMIN), 1, PLEN)
 
 	Return (MCRS)
@@ -198,7 +198,7 @@ Device (PDRC)
 
 	Name (PDRS, ResourceTemplate() {
 		Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
-		Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
+		Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
 		Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
 		Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
 		Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)
@@ -247,7 +247,7 @@ Device (IOSF)
 	Method (_CRS)
 	{
 		CreateDwordField (^RBUF, ^RBAR._BAS, RBAS)
-		Store (Add (CONFIG_MMCONF_BASE_ADDRESS, 0xD0), RBAS)
+		Store (Add (CONFIG_ECAM_MMCONF_BASE_ADDRESS, 0xD0), RBAS)
 		Return (^RBUF)
 	}
 }
diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c
index fa8283c9f2..3f07a6b439 100644
--- a/src/soc/intel/baytrail/bootblock/bootblock.c
+++ b/src/soc/intel/baytrail/bootblock/bootblock.c
@@ -89,7 +89,7 @@ static void setup_mmconfig(void)
 	reg = 0;
 	/* Clear the extended register. */
 	pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg);
-	reg = CONFIG_MMCONF_BASE_ADDRESS | 1;
+	reg = CONFIG_ECAM_MMCONF_BASE_ADDRESS | 1;
 	pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg);
 	reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) |
 	      IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN;
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 8ccf0432bc..f297b8f7a3 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -54,10 +54,10 @@ config VBOOT
 	select VBOOT_MUST_REQUEST_DISPLAY
 	select VBOOT_STARTS_IN_ROMSTAGE
 
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
 	default 0xe0000000
 
-config MMCONF_BUS_NUMBER
+config ECAM_MMCONF_BUS_NUMBER
 	int
 	default 256
 
diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl
index 01d1bc076d..8e765de4ff 100644
--- a/src/soc/intel/braswell/acpi/southcluster.asl
+++ b/src/soc/intel/braswell/acpi/southcluster.asl
@@ -146,7 +146,7 @@ Method (_CRS, 0, Serialized)
 				0x00000000, 0x20000000, 0x201FFFFF, 0x00000000,
 				0x00200000,,, LMEM)
 
-		/* PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) */
+		/* PCI Memory Region (Top of memory-CONFIG_ECAM_MMCONF_BASE_ADDRESS) */
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,
 				0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -183,7 +183,7 @@ Method (_CRS, 0, Serialized)
 
 	/* TOLM is BMBOUND accessible from IOSF so is saved in NVS */
 	Store (\TOLM, PMIN)
-	Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX)
+	Store (Subtract(CONFIG_ECAM_MMCONF_BASE_ADDRESS, 1), PMAX)
 	Add (Subtract (PMAX, PMIN), 1, PLEN)
 
 	Return (MCRS)
@@ -197,7 +197,7 @@ Device (PDRC)
 
 	Name (PDRS, ResourceTemplate() {
 		Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
-		Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
+		Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
 		Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
 		Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
 		Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)
@@ -246,7 +246,7 @@ Device (IOSF)
 	Method (_CRS)
 	{
 		CreateDwordField (^RBUF, ^RBAR._BAS, RBAS)
-		Store (Add (CONFIG_MMCONF_BASE_ADDRESS, 0xD0), RBAS)
+		Store (Add (CONFIG_ECAM_MMCONF_BASE_ADDRESS, 0xD0), RBAS)
 		Return (^RBUF)
 	}
 }
diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c
index ae1c97a9c4..545642f608 100644
--- a/src/soc/intel/braswell/bootblock/bootblock.c
+++ b/src/soc/intel/braswell/bootblock/bootblock.c
@@ -100,7 +100,7 @@ static void setup_mmconfig(void)
 	reg = 0;
 	/* Clear the extended register. */
 	pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg);
-	reg = CONFIG_MMCONF_BASE_ADDRESS | 1;
+	reg = CONFIG_ECAM_MMCONF_BASE_ADDRESS | 1;
 	pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg);
 	reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) |
 	      IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN;
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index f02e810b23..766c226dc4 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -33,10 +33,10 @@ config VBOOT
 	select VBOOT_MUST_REQUEST_DISPLAY
 	select VBOOT_STARTS_IN_ROMSTAGE if !BROADWELL_VBOOT_IN_BOOTBLOCK
 
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
 	default 0xf0000000
 
-config MMCONF_BUS_NUMBER
+config ECAM_MMCONF_BUS_NUMBER
 	default 64
 
 config VGA_BIOS_ID
diff --git a/src/soc/intel/broadwell/bootblock.c b/src/soc/intel/broadwell/bootblock.c
index bd88195d7f..8c851cac5d 100644
--- a/src/soc/intel/broadwell/bootblock.c
+++ b/src/soc/intel/broadwell/bootblock.c
@@ -8,7 +8,7 @@
 
 static uint32_t encode_pciexbar_length(void)
 {
-	switch (CONFIG_MMCONF_BUS_NUMBER) {
+	switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
 		case 256: return 0 << 1;
 		case 128: return 1 << 1;
 		case  64: return 2 << 1;
@@ -20,15 +20,15 @@ void bootblock_early_northbridge_init(void)
 {
 	/*
 	 * The "io" variant of the config access is explicitly used to setup the
-	 * PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to true. That way, all
+	 * PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to true. That way, all
 	 * subsequent non-explicit config accesses use MCFG. This code also assumes
 	 * that bootblock_northbridge_init() is the first thing called in the non-asm
 	 * boot block code. The final assumption is that no assembly code is using the
-	 * CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
+	 * CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses.
 	 *
 	 * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
 	 */
-	const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
+	const uint32_t reg = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
 	pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0);
 	pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg);
 }
diff --git a/src/soc/intel/broadwell/pei_data.c b/src/soc/intel/broadwell/pei_data.c
index c8fbfcadf7..db41b4bcc4 100644
--- a/src/soc/intel/broadwell/pei_data.c
+++ b/src/soc/intel/broadwell/pei_data.c
@@ -15,7 +15,7 @@ void broadwell_fill_pei_data(struct pei_data *pei_data)
 	pei_data->pei_version = PEI_VERSION;
 	pei_data->board_type = BOARD_TYPE_ULT;
 	pei_data->usbdebug = CONFIG(USBDEBUG);
-	pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS;
+	pei_data->pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
 	pei_data->smbusbar = CONFIG_FIXED_SMBUS_IO_BASE;
 	pei_data->ehcibar = CONFIG_EHCI_BAR;
 	pei_data->xhcibar = 0xd7000000;
diff --git a/src/soc/intel/cannonlake/systemagent.c b/src/soc/intel/cannonlake/systemagent.c
index 0b5e8e3f95..a2bea45bf9 100644
--- a/src/soc/intel/cannonlake/systemagent.c
+++ b/src/soc/intel/cannonlake/systemagent.c
@@ -20,7 +20,7 @@
 void soc_add_fixed_mmio_resources(struct device *dev, int *index)
 {
 	static const struct sa_mmio_descriptor soc_fixed_resources[] = {
-		{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH,
+		{ PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
 				"PCIEXBAR" },
 		{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
 		{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig
index 315c0f55fe..e9519bc624 100644
--- a/src/soc/intel/common/block/systemagent/Kconfig
+++ b/src/soc/intel/common/block/systemagent/Kconfig
@@ -5,10 +5,10 @@ config SOC_INTEL_COMMON_BLOCK_SA
 
 if SOC_INTEL_COMMON_BLOCK_SA
 
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
 	default 0xe0000000
 
-config MMCONF_BUS_NUMBER
+config ECAM_MMCONF_BUS_NUMBER
 	default 256
 
 config SA_ENABLE_IMR
diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c
index 6808117598..a77b307f5d 100644
--- a/src/soc/intel/common/block/systemagent/systemagent_early.c
+++ b/src/soc/intel/common/block/systemagent/systemagent_early.c
@@ -29,7 +29,7 @@ void bootblock_systemagent_early_init(void)
 	pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg);
 
 	/* Get PCI Express Region Length */
-	switch (CONFIG_MMCONF_BUS_NUMBER) {
+	switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
 	case 256:
 		pciexbar_length = PCIEXBAR_LENGTH_256MB;
 		break;
@@ -42,7 +42,7 @@ void bootblock_systemagent_early_init(void)
 	default:
 		dead_code();
 	}
-	reg = CONFIG_MMCONF_BASE_ADDRESS | (pciexbar_length << 1)
+	reg = CONFIG_ECAM_MMCONF_BASE_ADDRESS | (pciexbar_length << 1)
 				| PCIEXBAR_PCIEXBAREN;
 	pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg);
 
diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index a84cf1eebd..0643384e91 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -44,10 +44,10 @@ config CPU_SPECIFIC_OPTIONS
 	select FSP_T_XIP if FSP_CAR
 	select FSP_M_XIP
 
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
 	default 0xe0000000
 
-config MMCONF_BUS_NUMBER
+config ECAM_MMCONF_BUS_NUMBER
 	int
 	default 256
 
diff --git a/src/soc/intel/denverton_ns/acpi/northcluster.asl b/src/soc/intel/denverton_ns/acpi/northcluster.asl
index 26a6f2ed95..e415dc4ea3 100644
--- a/src/soc/intel/denverton_ns/acpi/northcluster.asl
+++ b/src/soc/intel/denverton_ns/acpi/northcluster.asl
@@ -122,7 +122,7 @@ Device (PDRC)
 
 	Name (PDRS, ResourceTemplate() {
 		// PCIEXBAR memory range
-		Memory32Fixed(ReadOnly, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
+		Memory32Fixed(ReadOnly, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
 		// TSEG
 		Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, TSMB)
 	})
diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c
index 1aebab4f83..cb2503ae40 100644
--- a/src/soc/intel/denverton_ns/bootblock/bootblock.c
+++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c
@@ -74,8 +74,8 @@ static void sanity_check_pci_mmconf(void)
 		break;
 	}
 
-	assert(base == CONFIG_MMCONF_BASE_ADDRESS);
-	assert(length == CONFIG_MMCONF_BUS_NUMBER);
+	assert(base == CONFIG_ECAM_MMCONF_BASE_ADDRESS);
+	assert(length == CONFIG_ECAM_MMCONF_BUS_NUMBER);
 }
 
 void bootblock_soc_early_init(void)
diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
index e5e9a06287..c2200286d0 100644
--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
@@ -130,7 +130,7 @@ config PCR_BASE_ADDRESS
 	help
 	  This option allows you to select MMIO Base Address of sideband bus.
 
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
 	default 0xc0000000
 
 config CPU_BCLK_MHZ
diff --git a/src/soc/intel/elkhartlake/systemagent.c b/src/soc/intel/elkhartlake/systemagent.c
index aa9c87f2fd..02ede59068 100644
--- a/src/soc/intel/elkhartlake/systemagent.c
+++ b/src/soc/intel/elkhartlake/systemagent.c
@@ -19,7 +19,7 @@
 void soc_add_fixed_mmio_resources(struct device *dev, int *index)
 {
 	static const struct sa_mmio_descriptor soc_fixed_resources[] = {
-		{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH,
+		{ PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
 				"PCIEXBAR" },
 		{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
 		{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index fcc0bfab8f..e99832d1ed 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -118,7 +118,7 @@ config PCR_BASE_ADDRESS
 	help
 	  This option allows you to select MMIO Base Address of sideband bus.
 
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
 	default 0xc0000000
 
 config CPU_BCLK_MHZ
diff --git a/src/soc/intel/icelake/systemagent.c b/src/soc/intel/icelake/systemagent.c
index 2f0b706317..4a24d3911f 100644
--- a/src/soc/intel/icelake/systemagent.c
+++ b/src/soc/intel/icelake/systemagent.c
@@ -15,7 +15,7 @@
 void soc_add_fixed_mmio_resources(struct device *dev, int *index)
 {
 	static const struct sa_mmio_descriptor soc_fixed_resources[] = {
-		{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH,
+		{ PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
 				"PCIEXBAR" },
 		{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
 		{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index 03f47056c8..7a73d989f2 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -126,7 +126,7 @@ config PCR_BASE_ADDRESS
 	help
 	  This option allows you to select MMIO Base Address of sideband bus.
 
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
 	default 0xc0000000
 
 config CPU_BCLK_MHZ
diff --git a/src/soc/intel/jasperlake/systemagent.c b/src/soc/intel/jasperlake/systemagent.c
index 45a83bceb4..fd04be589f 100644
--- a/src/soc/intel/jasperlake/systemagent.c
+++ b/src/soc/intel/jasperlake/systemagent.c
@@ -19,7 +19,7 @@
 void soc_add_fixed_mmio_resources(struct device *dev, int *index)
 {
 	static const struct sa_mmio_descriptor soc_fixed_resources[] = {
-		{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH,
+		{ PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
 				"PCIEXBAR" },
 		{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
 		{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index 1a9bfef942..ad885d5f6d 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -10,7 +10,7 @@ if SOC_INTEL_QUARK
 config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select ARCH_X86
-	select NO_MMCONF_SUPPORT
+	select NO_ECAM_MMCONF_SUPPORT
 	select REG_SCRIPT
 	select PLATFORM_USES_FSP2_0
 	select SOC_INTEL_COMMON
diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c
index f11208720d..6186734d7e 100644
--- a/src/soc/intel/skylake/systemagent.c
+++ b/src/soc/intel/skylake/systemagent.c
@@ -34,7 +34,7 @@ bool soc_vtd_enabled(void)
 void soc_add_fixed_mmio_resources(struct device *dev, int *index)
 {
 	static const struct sa_mmio_descriptor soc_fixed_resources[] = {
-		{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH,
+		{ PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
 				"PCIEXBAR" },
 		{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
 		{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 33e8b134fb..91f33161b4 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -161,7 +161,7 @@ config PCR_BASE_ADDRESS
 	help
 	  This option allows you to select MMIO Base Address of sideband bus.
 
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
 	default 0xc0000000
 
 config CPU_BCLK_MHZ
diff --git a/src/soc/intel/tigerlake/systemagent.c b/src/soc/intel/tigerlake/systemagent.c
index f1aa60011b..0e9488c1b2 100644
--- a/src/soc/intel/tigerlake/systemagent.c
+++ b/src/soc/intel/tigerlake/systemagent.c
@@ -27,7 +27,7 @@
 void soc_add_fixed_mmio_resources(struct device *dev, int *index)
 {
 	static const struct sa_mmio_descriptor soc_fixed_resources[] = {
-		{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH,
+		{ PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
 				"PCIEXBAR" },
 		{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
 		{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index fa8403a235..d912f1776f 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -103,10 +103,10 @@ config DCACHE_BSP_STACK_SIZE
 	hex
 	default 0x10000
 
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
 	default 0x80000000
 
-config MMCONF_BUS_NUMBER
+config ECAM_MMCONF_BUS_NUMBER
 	default 256
 
 config HEAP_SIZE
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c
index 4f509809d7..e51efbd693 100644
--- a/src/soc/intel/xeon_sp/uncore.c
+++ b/src/soc/intel/xeon_sp/uncore.c
@@ -137,7 +137,7 @@ static void configure_dpr(struct device *dev)
  * |     P2SB PCR cfg BAR     | (0xfd000000 - 0xfdffffff
  * |     BAR space            | [mem 0x90000000-0xfcffffff] available for PCI devices
  * +--------------------------+ 0x9000_0000
- * |PCIe MMCFG (relocatable)  | CONFIG_MMCONF_BASE_ADDRESS 64 or 256MB
+ * |PCIe MMCFG (relocatable)  | CONFIG_ECAM_MMCONF_BASE_ADDRESS 64 or 256MB
  * |                          | (0x80000000 - 0x8fffffff, 0x40000)
  * +--------------------------+ TOLM
  * |     MEseg (relocatable)  | 32, 64, 128 or 256 MB (0x78000000 - 0x7fffffff, 0x20000)