soc/intel: Abstract the common block API for TCSS registers access

The existing TCSS registers access is through the REGBAR. There will be
future platforms which access the TCSS registers through the Sideband
interface. This change abstracts the common block API for TCSS access.

BUG=b:213574324
TEST=Build platforms coreboot images successfully.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I3e2696b117af24412d73b257f470efc40caa5022
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>

7 files changed, 49 insertions, 11 deletions

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index ac8c2e3843..89d0c93791 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -87,6 +87,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_SMM
 	select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
 	select SOC_INTEL_COMMON_BLOCK_TCSS
+	select SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_REGBAR
 	select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC
 	select SOC_INTEL_COMMON_BLOCK_USB4
 	select SOC_INTEL_COMMON_BLOCK_USB4_PCIE
diff --git a/src/soc/intel/common/block/include/intelblocks/tcss.h b/src/soc/intel/common/block/include/intelblocks/tcss.h
index e5834b08c6..181eff0bf8 100644
--- a/src/soc/intel/common/block/include/intelblocks/tcss.h
+++ b/src/soc/intel/common/block/include/intelblocks/tcss.h
@@ -151,4 +151,7 @@ void tcss_configure(const struct typec_aux_bias_pads pads[MAX_TYPE_C_PORTS]);
  */
 const struct tcss_port_map *tcss_get_port_info(size_t *num_ports);
 
+/* Method to validate the Thunderbolt authentication */
+uint32_t tcss_valid_tbt_auth(void);
+
 #endif /* _TCSS_H_ */
diff --git a/src/soc/intel/common/block/tcss/Kconfig b/src/soc/intel/common/block/tcss/Kconfig
index 2e679138cd..0b80cb951f 100644
--- a/src/soc/intel/common/block/tcss/Kconfig
+++ b/src/soc/intel/common/block/tcss/Kconfig
@@ -9,3 +9,16 @@ config ENABLE_TCSS_DISPLAY_DETECTION
 	depends on SOC_INTEL_COMMON_BLOCK_TCSS && RUN_FSP_GOP
 	help
 	  Enable displays to be detected over Type-C ports during boot.
+
+config SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_REGBAR
+	def_bool n
+	depends on SOC_INTEL_COMMON_BLOCK_TCSS
+	help
+	  Enable TCSS registers access through REGBAR for platforms like
+	  Tiger Lake and Alder Lake
+
+config SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_SBI
+	def_bool n
+	depends on SOC_INTEL_COMMON_BLOCK_TCSS
+	help
+	  Enable TCSS registers access through Sideband interface on applicable SoC platforms
diff --git a/src/soc/intel/common/block/tcss/tcss.c b/src/soc/intel/common/block/tcss/tcss.c
index 3e11865848..2531ac3942 100644
--- a/src/soc/intel/common/block/tcss/tcss.c
+++ b/src/soc/intel/common/block/tcss/tcss.c
@@ -1,8 +1,12 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#define __SIMPLE_DEVICE__
+
 #include <bootmode.h>
 #include <console/console.h>
 #include <device/pci.h>
+#include <intelblocks/p2sb.h>
+#include <intelblocks/pcr.h>
 #include <intelblocks/pmc_ipc.h>
 #include <intelblocks/systemagent.h>
 #include <intelblocks/tcss.h>
@@ -351,8 +355,8 @@ static uint32_t calc_bias_ctrl_reg_value(gpio_t pad)
 		cpu_pid;
 }
 
-static void tcss_configure_aux_bias_pads(
-	const struct typec_aux_bias_pads pads[MAX_TYPE_C_PORTS])
+static void tcss_configure_aux_bias_pads_regbar(
+	const struct typec_aux_bias_pads *pads)
 {
 	for (size_t i = 0; i < MAX_TYPE_C_PORTS; i++) {
 		if (pads[i].pad_auxn_dc && pads[i].pad_auxp_dc) {
@@ -364,6 +368,16 @@ static void tcss_configure_aux_bias_pads(
 	}
 }
 
+static void tcss_configure_aux_bias_pads(
+	const struct typec_aux_bias_pads *pads)
+{
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_REGBAR))
+		tcss_configure_aux_bias_pads_regbar(pads);
+	else
+		printk(BIOS_ERR, "%s: Error: No TCSS configuration method is selected!\n",
+					__func__);
+}
+
 const struct tcss_port_map *tcss_get_port_info(size_t *num_ports)
 {
 	static struct tcss_port_map port_map[MAX_TYPE_C_PORTS];
@@ -414,3 +428,14 @@ void tcss_configure(const struct typec_aux_bias_pads aux_bias_pads[MAX_TYPE_C_PO
 	if (CONFIG(ENABLE_TCSS_DISPLAY_DETECTION))
 		tcss_configure_dp_mode(port_map, num_ports);
 }
+
+uint32_t tcss_valid_tbt_auth(void)
+{
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_REGBAR)) {
+		return REGBAR32(PID_IOM, IOM_CSME_IMR_TBT_STATUS) & TBT_VALID_AUTHENTICATION;
+	} else {
+		printk(BIOS_ERR, "%s: Error: No validation for Thunderbolt authentication!\n",
+					__func__);
+		return 0;
+	}
+}
diff --git a/src/soc/intel/common/block/usb4/Kconfig b/src/soc/intel/common/block/usb4/Kconfig
index bc1eb19d49..05337be0da 100644
--- a/src/soc/intel/common/block/usb4/Kconfig
+++ b/src/soc/intel/common/block/usb4/Kconfig
@@ -1,6 +1,7 @@
 config SOC_INTEL_COMMON_BLOCK_USB4
 	bool
 	default n
+	depends on SOC_INTEL_COMMON_BLOCK_TCSS
 	help
 	  Minimal PCI Driver for enabling SSDT generation for the DMA component
 	  of Intel Thunderbolt/USB4 ports.
diff --git a/src/soc/intel/common/block/usb4/usb4.c b/src/soc/intel/common/block/usb4/usb4.c
index 8b1609d140..0ec4d5fdf3 100644
--- a/src/soc/intel/common/block/usb4/usb4.c
+++ b/src/soc/intel/common/block/usb4/usb4.c
@@ -6,10 +6,8 @@
 #include <device/pci.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
-#include <intelblocks/systemagent.h>
+#include <intelblocks/tcss.h>
 #include <soc/pci_devs.h>
-#include <soc/pcr_ids.h>
-#include <soc/tcss.h>
 
 #define INTEL_TBT_IMR_VALID_UUID	"C44D002F-69F9-4E7D-A904-A7BAABDF43F7"
 #define INTEL_TBT_WAKE_SUPPORTED_UUID	"6C501103-C189-4296-BA72-9BF5A26EBE5D"
@@ -27,16 +25,11 @@ static const char *tbt_dma_acpi_name(const struct device *dev)
 	}
 }
 
-static int valid_tbt_auth(void)
-{
-	return REGBAR32(PID_IOM, IOM_CSME_IMR_TBT_STATUS) & TBT_VALID_AUTHENTICATION;
-}
-
 static void tbt_dma_fill_ssdt(const struct device *dev)
 {
 	struct acpi_dp *dsd, *pkg;
 
-	if (!valid_tbt_auth())
+	if (!tcss_valid_tbt_auth())
 		return;
 
 	acpigen_write_scope(acpi_device_path(dev));
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 3ef1005efa..b324a048d4 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -67,6 +67,8 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_SA
 	select SOC_INTEL_COMMON_BLOCK_SMM
 	select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
+	select SOC_INTEL_COMMON_BLOCK_TCSS
+	select SOC_INTEL_COMMON_BLOCK_TCSS_REG_ACCESS_REGBAR
 	select SOC_INTEL_COMMON_BLOCK_USB4
 	select SOC_INTEL_COMMON_BLOCK_USB4_PCIE
 	select SOC_INTEL_COMMON_BLOCK_USB4_XHCI