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authorRaul E Rangel <rrangel@chromium.org>2021-04-06 15:41:22 -0600
committerPatrick Georgi <pgeorgi@google.com>2021-04-08 06:48:22 +0000
commit2ff76be15cf21b8e9af298e797ee75732af31838 (patch)
treed68f00bee66eb88ecdbbdb1e1849608d1279d1a8 /src/soc
parent3db49929bd7d755aad920ae6b8757bba57864989 (diff)
soc/amd/common: Add PM_ESPI_INTR_CTRL
This register is used for masking/unmasking eSPI IRQs. BUG=none TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia209539b2e0ce390e227757b16c2969b9124a845 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52142 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/common/block/include/amdblocks/acpimmio.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
index 9360650851..9c007e7668 100644
--- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h
+++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h
@@ -26,6 +26,8 @@
#define LEGACY_DMA_IO_EN (1 << 2)
#define CF9_IO_EN (1 << 1)
#define LEGACY_IO_EN (1 << 0)
+#define PM_ESPI_INTR_CTRL 0x40
+#define PM_ESPI_DEV_INTR_MASK 0x00FFFFFF
#define PM_RST_CTRL1 0xbe
#define SLPTYPE_CONTROL_EN (1 << 5)
#define KBRSTEN (1 << 4)