diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2023-07-21 07:45:54 +0200 |
|---|---|---|
| committer | Elyes Haouas <ehaouas@noos.fr> | 2023-08-03 18:29:27 +0000 |
| commit | 2e52f0e2438a35f7cffd7ca802a4a0966e02297c (patch) | |
| tree | 9c2354caf5cbde57a877c5ef7fc7edbc2f523a2d /src/soc | |
| parent | a56a5c2cf8e6db4b35dcfb333050f8352d9cd51e (diff) | |
soc/intel/skylake: Remove dummy CPU_SPECIFIC_OPTIONS
Change-Id: Iea0e55c6c55635976dad0422470f3927bdc26e35
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/skylake/Kconfig | 39 |
1 files changed, 18 insertions, 21 deletions
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index e15af04b65..d6a11363ee 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -1,26 +1,5 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE bool - -config SOC_INTEL_SKYLAKE - bool - select SOC_INTEL_COMMON_SKYLAKE_BASE - -config SOC_INTEL_KABYLAKE - bool - select SOC_INTEL_COMMON_SKYLAKE_BASE - -config SOC_INTEL_SKYLAKE_LGA1151_V2 - bool - select PLATFORM_USES_FSP2_1 - select SOC_INTEL_COMMON_SKYLAKE_BASE - select SKYLAKE_SOC_PCH_H - help - Selected by mainboards with a LGA1151 v2 socket and a Z370, H310C or B365 PCH - -if SOC_INTEL_COMMON_SKYLAKE_BASE - -config CPU_SPECIFIC_OPTIONS - def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_NHLT select ARCH_X86 @@ -92,6 +71,24 @@ config CPU_SPECIFIC_OPTIONS select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE +config SOC_INTEL_SKYLAKE + bool + select SOC_INTEL_COMMON_SKYLAKE_BASE + +config SOC_INTEL_KABYLAKE + bool + select SOC_INTEL_COMMON_SKYLAKE_BASE + +config SOC_INTEL_SKYLAKE_LGA1151_V2 + bool + select PLATFORM_USES_FSP2_1 + select SOC_INTEL_COMMON_SKYLAKE_BASE + select SKYLAKE_SOC_PCH_H + help + Selected by mainboards with a LGA1151 v2 socket and a Z370, H310C or B365 PCH + +if SOC_INTEL_COMMON_SKYLAKE_BASE + config MAX_HECI_DEVICES int default 5 |