diff options
| author | Yidi Lin <yidilin@chromium.org> | 2022-12-05 16:24:57 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-09 17:07:00 +0000 |
| commit | 28188e3e8b32ef78bfc755326cf6e9efa0ef6ad9 (patch) | |
| tree | 63bacc0142f0600906bc41855d1fc336acb3bfa0 /src/soc | |
| parent | 68bbbf8db2b59b7096eeb04be1d0a1d11fa2ea23 (diff) | |
soc/mediatek/mt8173: Allow BL31 payload not targeting RAM
selfboot.c blocks the payload that does not target RAM. But MT8173 loads
and runs BL31 payload in SRAM. Make the exception by implementing
`payload_arch_usable_ram_quirk()`.
TEST=load and initialize BL31 successfully
Change-Id: I8951b1c4673cdae7d1ad0c11d7d6c12376acd328
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70344
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/mediatek/mt8173/soc.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8173/soc.c b/src/soc/mediatek/mt8173/soc.c index c1bb6212d1..ebdf4e5420 100644 --- a/src/soc/mediatek/mt8173/soc.c +++ b/src/soc/mediatek/mt8173/soc.c @@ -2,9 +2,23 @@ #include <bootmem.h> #include <device/device.h> +#include <program_loading.h> #include <symbols.h> #include <soc/emi.h> +int payload_arch_usable_ram_quirk(uint64_t start, uint64_t size) +{ + if (size > REGION_SIZE(sram)) + return 0; + + if (start >= (uintptr_t)_sram && (start + size) <= (uintptr_t)_esram) { + printk(BIOS_DEBUG, "MT8173 uses SRAM for loading BL31.\n"); + return 1; + } + + return 0; +} + void bootmem_platform_add_ranges(void) { bootmem_add_range(0x101000, 124 * KiB, BM_MEM_BL31); |