diff options
| author | Subrata Banik <subratabanik@google.com> | 2023-09-02 19:16:52 +0000 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-09-04 05:37:15 +0000 |
| commit | 1b96bff27ea98593f28e1bd60b3ee8e727841d2a (patch) | |
| tree | cf9e05b8dc6c7a86be2bbeaffec07bee6ec6d367 /src/soc | |
| parent | 5c35d30ffc7382af46b62044a5cf5326b1e57708 (diff) | |
{drivers/intel/fsp2_0, soc/intel}: Rename `SAVE_MRC_AFTER_FSPS` config
This patch renames `SAVE_MRC_AFTER_FSPS` config to
`FSP_NVS_DATA_POST_SILICON_INIT` to highlight the violation in the Xeon
SP FSP implementation, where the FSP Silicon Init API produces
Non-Volatile Storage (NVS) instead of the FSP-Memory Init API.
According to the FSP 2.x specification (section 11.3), the FSP
populates the NVS data using the FSP_NON_VOLATILE_STORAGE_HOB and
expects the boot firmware to parse the FSP_NON_VOLATILE_STORAGE_HOB
after the FspMemoryInit() API in API mode.
However, not all Intel SoC platforms that support the FSP 2.x
specification adhere to this requirement. For example, the FSP binary
for XEON SP platform produces NVS data (aka
FSP_NON_VOLATILE_STORAGE_HOB) after the FspSiliconInit() API.
Therefore, attempting to locate NVS data after the FspMemoryInit() API
on these platforms would result in an error. The `save_mrc_data.c`
implementation provides the required hooks to locate the NVS post
FSP-Silicon Init and store into Non-Volatile Storage.
BUG=b:296704537
TEST=Able to build and boot Intel Xeon SP w/o any functional impact.
Change-Id: I815a64263fa1415bfe30bb3c1c35e4adee307e86
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index 9c19f3b1cc..dac093f9d2 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -2,8 +2,8 @@ config SOC_INTEL_SAPPHIRERAPIDS_SP bool + select FSP_NVS_DATA_POST_SILICON_INIT select MICROCODE_BLOB_NOT_HOOKED_UP - select SAVE_MRC_AFTER_FSPS select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select DISABLE_ACPI_HIBERNATE select DEFAULT_X2APIC_RUNTIME |