diff options
| author | Hannah Williams <hannah.williams@intel.com> | 2017-11-21 12:11:30 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-12-08 23:24:23 +0000 |
| commit | 11f7dc87b2df7e84583f63d49df3660cc02b223f (patch) | |
| tree | fa016b27c29c6180f0ff744ae7f332b98b8d647c /src/soc | |
| parent | cbae0cc931d5027b9776fdf93dae531d81372c7a (diff) | |
soc/intel/apollolake/acpi/cnvi.asl: Add _PRW for CNVi
Add CNVi GPE in _PRW for wake on WLAN from S3
Change-Id: I682c76b9c5c524face7b540ecb185a3d7b4b2da3
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/22639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/apollolake/acpi/cnvi.asl | 30 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/acpi/southbridge.asl | 6 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/gpe.h | 1 |
3 files changed, 37 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/acpi/cnvi.asl b/src/soc/intel/apollolake/acpi/cnvi.asl new file mode 100644 index 0000000000..a4d255dc1f --- /dev/null +++ b/src/soc/intel/apollolake/acpi/cnvi.asl @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* CNVi Controller 0:C.0 */ +Device (CNVI) { + Name(_ADR, 0x000C0000) + + Name (_S3D, 3) /* D3 supported in S3 */ + Name (_S0W, 3) /* D3 can wake device in S0 */ + Name (_S3W, 3) /* D3 can wake system from S3 */ + + Name (_PRW, Package() { GPE0A_CNVI_PME_STS, 3 }) + + Method (_STA, 0) + { + Return (0xF) + } +} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 97a25a296f..5b8f9b7aa6 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -56,4 +56,10 @@ Scope (\_SB) /* SGX */ #if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX) #include <soc/intel/common/acpi/sgx.asl> + +/* CNVi */ +#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#include "cnvi.asl" +#endif + #endif diff --git a/src/soc/intel/apollolake/include/soc/gpe.h b/src/soc/intel/apollolake/include/soc/gpe.h index 7dfb6f5bd2..eb6e31f47a 100644 --- a/src/soc/intel/apollolake/include/soc/gpe.h +++ b/src/soc/intel/apollolake/include/soc/gpe.h @@ -33,6 +33,7 @@ #define GPE0A_GPIO_TIER1_SCI_STS 15 #define GPE0A_SMB_WAK_STS 16 #define GPE0A_SATA_PME_STS 17 +#define GPE0A_CNVI_PME_STS 18 /* Group DW0 is reserved in Apollolake */ |