diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-12-09 13:31:47 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-12-14 06:35:11 +0000 |
| commit | 10929ef008f433ce3a500b79534016bfa8456196 (patch) | |
| tree | fd73081808b92a47eee353e2617a250c2553e193 /src/soc | |
| parent | b25aeb59379d04f4ad6e120e729286a341d301c8 (diff) | |
soc/intel/meteorlake: Fill ucode loading UPD if USE_FSP_MP_INIT enable
This patch calls into a helper function to fill `2nd microcode loading
FSP UPD` if FSP is running CPU feature programming.
This patch is backported from
commit fad1cb062e29c5e3a5bcfb6b67c3ce01ed765254 (soc/intel/alderlake:
Fill ucode loading UPD if USE_FSP_MP_INIT enable).
Change-Id: Id8c8bfd844b3213cc260df20c359b0b1437e3e28
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70599
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/meteorlake/fsp_params.c | 27 |
1 files changed, 20 insertions, 7 deletions
diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index 4058dda287..954e2e0d48 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -4,6 +4,7 @@ #include <cbfs.h> #include <console/console.h> #include <cpu/intel/cpu_ids.h> +#include <cpu/intel/microcode.h> #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> @@ -119,23 +120,35 @@ static void fill_fsps_lpss_params(FSP_S_CONFIG *s_cfg, } } -static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, +static void fill_fsps_microcode_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_meteorlake_config *config) { const struct microcode *microcode_file; size_t microcode_len; /* Locate microcode and pass to FSP-S for 2nd microcode loading */ - microcode_file = cbfs_map("cpu_microcode_blob.bin", µcode_len); - - if ((microcode_file) && (microcode_len != 0)) { - /* Update CPU Microcode patch base address/size */ - s_cfg->MicrocodeRegionBase = (uint32_t)microcode_file; - s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len; + microcode_file = intel_microcode_find(); + + if (microcode_file != NULL) { + microcode_len = get_microcode_size(microcode_file); + if (microcode_len != 0) { + /* Update CPU Microcode patch base address/size */ + s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode_file; + s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len; + } } +} +static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, + const struct soc_intel_meteorlake_config *config) +{ if (CONFIG(MTL_USE_FSP_MP_INIT)) { /* + * Fill `2nd microcode loading FSP UPD` if FSP is running CPU feature + * programming. + */ + fill_fsps_microcode_params(s_cfg, config); + /* * Use FSP running MP PPI services to perform CPU feature programming * if Kconfig is enabled */ |