diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-05-03 10:59:45 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2021-05-05 15:14:46 +0000 |
| commit | 0f068a600ebca71d5bf175ad70115ffbd679b3c3 (patch) | |
| tree | a45fdf455e70a6aed497616ad693459bcac1fc82 /src/soc | |
| parent | be2f937f1ef51cb791739eae1fc00c441bb06860 (diff) | |
drivers/intel/fsp2_0: Fix the FSP-T position
The only use case for FSP-T in coreboot is for 'Intel Bootguard'
support at the moment. Bootguard can do verification FSP-T but there
is no verification on whether the FSP found by walkcbfs_asm is the one
actually verified as an IBB by Bootguard. A fixed pointer needs to be
used.
TESTED on OCP/Deltalake, still boots.
Change-Id: I1ec8b238384684dccf39e5da902d426d3a32b9db
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S | 11 |
1 files changed, 1 insertions, 10 deletions
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index a2e85b9aac..173ebf7699 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -21,16 +21,7 @@ bootblock_pre_c_entry: cache_as_ram: post_code(0x21) - /* find fsp in cbfs */ - lea fsp_name, %esi - mov $1f, %esp - jmp walkcbfs_asm -1: - cmp $0, %eax - jz .halt_forever - mov CBFS_FILE_OFFSET(%eax), %ebx - bswap %ebx - add %eax, %ebx + movl $(CONFIG_FSP_T_LOCATION), %ebx add $0x94, %ebx /* |