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authorFelix Held <felix-coreboot@felixheld.de>2023-02-03 17:03:20 +0100
committerFelix Held <felix-coreboot@felixheld.de>2023-02-04 20:26:30 +0000
commit0cf73ab9fd9dcbc366037948396145710406ef6c (patch)
tree97cc1eeeff6f6e4ce18f5e492c3e1faf20a86e05 /src/soc
parenta35b9282cf3bfcc416a17659b846a33ad5458e1c (diff)
soc/amd/phoenix/chipset.cb: add remaining PCI devices
The PCI Device ID Assignments table from PPRs #57019 Rev 1.65 and PPR #57396 Rev 1.54 were used as a reference. Some devices will need to have ops added in future patches. Since the xhci_2 device isn't there any more, also drop it from the mainboard devicetrees. The actual USB port configuration on xhci_0 and xhci_1 is updated in the next patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I49721bc44fa1e2a0118a8c3ac79a36aee64be687 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/phoenix/chipset.cb20
1 files changed, 18 insertions, 2 deletions
diff --git a/src/soc/amd/phoenix/chipset.cb b/src/soc/amd/phoenix/chipset.cb
index f1c32faf1b..5763be88b1 100644
--- a/src/soc/amd/phoenix/chipset.cb
+++ b/src/soc/amd/phoenix/chipset.cb
@@ -25,6 +25,12 @@ chip soc/amd/phoenix
device pci 02.5 alias gpp_bridge_2_5 off ops amd_external_pcie_gpp_ops end
device pci 02.6 alias gpp_bridge_2_6 off ops amd_external_pcie_gpp_ops end
+ device pci 03.0 on end # Dummy Host Bridge, do not disable
+ device pci 03.1 alias usb4_pcie_bridge_0 off end
+
+ device pci 04.0 on end # Dummy Host Bridge, do not disable
+ device pci 04.1 alias usb4_pcie_bridge_1 off end
+
device pci 08.0 on end # Dummy Host Bridge, do not disable
device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A
ops amd_internal_pcie_gpp_ops
@@ -73,10 +79,20 @@ chip soc/amd/phoenix
device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ)
device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2)
end
- device pci 08.2 alias gpp_bridge_b off ops amd_internal_pcie_gpp_ops end # Internal GPP Bridge 1 to Bus B
+ device pci 08.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B
+ ops amd_internal_pcie_gpp_ops
+ device pci 0.0 on end # dummy, do not disable
+ device pci 0.1 alias ipu off end
+ end
+
device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C
ops amd_internal_pcie_gpp_ops
- device pci 0.0 alias xhci_2 off end # Might also be a dummy device with different PCI DID
+ device pci 0.0 on end # dummy, do not disable
+ device pci 0.2 alias i2s_ac97 off end
+ device pci 0.3 alias usb4_xhci_0 off end
+ device pci 0.4 alias usb4_xhci_1 off end
+ device pci 0.5 alias usb4_router_0 off end
+ device pci 0.6 alias usb4_router_1 off end
end
device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function