diff options
| author | Naresh Solanki <Naresh.Solanki@9elements.com> | 2023-07-17 15:52:55 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-07-25 13:21:16 +0000 |
| commit | 0a12d2bdc848098b6f44f75b9289931405cb53b4 (patch) | |
| tree | ba0682a2169167721bc41c4ee7646c9a52ee01d1 /src/soc | |
| parent | 6e0de5d9cc8ba6aefc5407f91a6c00781d19ab8e (diff) | |
soc/intel/xeon/spr: Improve RMT configuration
Set AllowedSocketsInParallel to 1 for RMT builds.
This help in associating any failures encountered during RMT run
with the corresponding Socket/MC/DIMM.
Intel recommended setting EnforcePopulationPor to 1 for RMT runs
for debugging failures if any.
Change-Id: Ie2301368e9470cc23171c3c4eca9fe978e1513d4
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76679
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/romstage.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index 8004730c59..0443df1f60 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -223,6 +223,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mupd->FspmConfig.EnableRMT = 0x1; /* Set FSP debug message to Max for RMT logs */ mupd->FspmConfig.serialDebugMsgLvl = 0x3; + mupd->FspmConfig.AllowedSocketsInParallel = 0x1; + mupd->FspmConfig.EnforcePopulationPor = 0x1; } } |