vboot: reset vbnv in cmos when cmos failure occurs

There's an occasional issue on machines which use CMOS for their
vbnv storage. The machine that just powers up from complete G3
would have had their RTC rail not held up. The contents of vbnv
in CMOS could pass the crc8 though the values could be bad. In
order to fix this introduce two functions:

1. vbnv_init_cmos()
2. vbnv_cmos_failed()

At the start of vboot the CMOS is queried for failure. If there
is a failure indicated then the vbnv data is restored from flash
backup or reset to known values when there is no flash backup.

BUG=b:63054105

Change-Id: I8bd6f28f64a116b84a08ce4779cd4dc73c0f2f3d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

8 files changed, 62 insertions, 0 deletions

diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index b6669f1cef..06d9f5820d 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -41,6 +41,7 @@ bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c
 bootblock-y += fixme.c
 bootblock-y += bootblock/bootblock.c
 bootblock-y += early_setup.c
+bootblock-y += pmutil.c
 bootblock-y += tsc_freq.c
 
 romstage-y += romstage.c
@@ -50,12 +51,14 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
 romstage-y += fixme.c
 romstage-y += gpio.c
 romstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c
+romstage-y += pmutil.c
 romstage-y += smbus.c
 romstage-y += smbus_spd.c
 romstage-y += ramtop.c
 romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
 romstage-y += tsc_freq.c
 
+verstage-y += pmutil.c
 verstage-y += reset.c
 verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
 verstage-y += tsc_freq.c
@@ -71,6 +74,7 @@ ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += imc.c
 ramstage-y += lpc.c
 ramstage-y += model_15_init.c
 ramstage-y += northbridge.c
+ramstage-y += pmutil.c
 ramstage-y += reset.c
 ramstage-y += sata.c
 ramstage-y += sm.c
diff --git a/src/soc/amd/stoneyridge/pmutil.c b/src/soc/amd/stoneyridge/pmutil.c
new file mode 100644
index 0000000000..5bbea2ac6b
--- /dev/null
+++ b/src/soc/amd/stoneyridge/pmutil.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <vboot/vbnv.h>
+
+int vbnv_cmos_failed(void)
+{
+	/* FIXME: RTC failure checking not supported. */
+	return 0;
+}
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index abf47b7782..666ef83763 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -34,6 +34,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <timer.h>
+#include <vboot/vbnv.h>
 #include "chip.h"
 
 static uintptr_t read_pmc_mmio_bar(void)
@@ -217,3 +218,8 @@ int soc_get_rtc_failed(void)
 
 	return rtc_failed(ps->gen_pmcon1);
 }
+
+int vbnv_cmos_failed(void)
+{
+	return rtc_failed(read32((void *)(read_pmc_mmio_bar() + GEN_PMCON1)));
+}
diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c
index ab2a4ba6d4..fbdea8f4da 100644
--- a/src/soc/intel/baytrail/pmutil.c
+++ b/src/soc/intel/baytrail/pmutil.c
@@ -22,6 +22,7 @@
 #include <soc/lpc.h>
 #include <soc/pci_devs.h>
 #include <soc/pmc.h>
+#include <vboot/vbnv.h>
 
 #if defined(__SIMPLE_DEVICE__)
 
@@ -378,3 +379,8 @@ int rtc_failure(void)
 
 	return rtc_fail;
 }
+
+int vbnv_cmos_failed(void)
+{
+	return rtc_failure();
+}
diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c
index 4154522d4e..b5f284ff95 100644
--- a/src/soc/intel/braswell/pmutil.c
+++ b/src/soc/intel/braswell/pmutil.c
@@ -23,6 +23,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <stdint.h>
+#include <vboot/vbnv.h>
 
 #if defined(__SIMPLE_DEVICE__)
 
@@ -374,3 +375,8 @@ int rtc_failure(void)
 
 	return rtc_fail;
 }
+
+int vbnv_cmos_failed(void)
+{
+	return rtc_failure();
+}
diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c
index 7cf184ee05..0edcd8c3a9 100644
--- a/src/soc/intel/broadwell/pmutil.c
+++ b/src/soc/intel/broadwell/pmutil.c
@@ -28,6 +28,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/gpio.h>
+#include <vboot/vbnv.h>
 
 /* Print status bits with descriptive names */
 static void print_status_bits(u32 status, const char *bit_names[])
@@ -463,3 +464,8 @@ int rtc_failure(void)
 
 	return !!rtc_failed;
 }
+
+int vbnv_cmos_failed(void)
+{
+	return rtc_failure();
+}
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c
index ebd3d61cc8..cee3f95a10 100644
--- a/src/soc/intel/cannonlake/pmutil.c
+++ b/src/soc/intel/cannonlake/pmutil.c
@@ -40,6 +40,7 @@
 #include <soc/pm.h>
 #include <soc/smbus.h>
 #include <timer.h>
+#include <vboot/vbnv.h>
 #include "chip.h"
 
 /*
@@ -207,3 +208,8 @@ int soc_get_rtc_failed(void)
 
 	return rtc_failed(ps->gen_pmcon_b);
 }
+
+int vbnv_cmos_failed(void)
+{
+	return rtc_failed(read32(pmc_mmio_regs() + GEN_PMCON_B));
+}
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index 6ab949ba57..2a677fda74 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -38,6 +38,7 @@
 #include <soc/pmc.h>
 #include <soc/smbus.h>
 #include <timer.h>
+#include <vboot/vbnv.h>
 #include "chip.h"
 
 /* Print status bits with descriptive names */
@@ -558,3 +559,8 @@ int rtc_failure(void)
 
 	return !!rtc_failed;
 }
+
+int vbnv_cmos_failed(void)
+{
+	return rtc_failure();
+}