diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-09-28 17:55:02 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-09-30 03:53:42 +0000 |
| commit | 063e933194ec9b41775f5e2f1a175f1c97657f1b (patch) | |
| tree | 152dc59e7f37a09ab9f81fa7950d1958ee8a150d /src/soc | |
| parent | e37e668e5a189e3344f9d6f1f89dce29f4fcd5f7 (diff) | |
soc/intel/skylake: Align PMC offset 0x31C name with CNL
As per EDS PMC BASE Offset 0x31C is known as CPPMVRIC hence rename
CIR31C with CPPMVRIC.
Change-Id: Idaff62fb742e6c58b1d8e662b5e4087fa2da79a3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45795
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/skylake/finalize.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/skylake/include/soc/pmc.h | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 98f12a5b6c..0294a725b2 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -81,9 +81,9 @@ static void pch_finalize_script(struct device *dev) /* Disable XTAL shutdown qualification for low power idle. */ if (config->s0ix_enable) { - reg32 = read32(pmcbase + CIR31C); + reg32 = read32(pmcbase + CPPMVRIC); reg32 |= XTALSDQDIS; - write32(pmcbase + CIR31C, reg32); + write32(pmcbase + CPPMVRIC, reg32); } /* we should disable Heci1 based on the devicetree policy */ diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h index f4995a2e86..68d9eb3d27 100644 --- a/src/soc/intel/skylake/include/soc/pmc.h +++ b/src/soc/intel/skylake/include/soc/pmc.h @@ -82,6 +82,6 @@ #define GPE0_DW_SHIFT(x) (4*(x)) #define GBLRST_CAUSE0 0x124 #define GBLRST_CAUSE1 0x128 -#define CIR31C 0x31c +#define CPPMVRIC 0x31c #define XTALSDQDIS (1 << 22) #endif |