soc/intel/common/pch: Add a block specific to Apollo Lake

Add SOC_INTEL_COMMON_PCH_CLIENT which is specific to Apollo
Lake. This is used to select the options that Apollo Lake
requires, without the ones specific to a PCH as Apollo Lake
doesn't have a PCH.

This change also enables SOC_INTEL_COMMON_PCH_LOCKDOWN for
Apollo Lake.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I084a05f904a19f3b7e9a071636659670aa45bf3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

4 files changed, 41 insertions, 27 deletions

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 36bc631bb9..b2c224646f 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -73,44 +73,23 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
 	select SOC_INTEL_COMMON_BLOCK_ACPI
 	select SOC_INTEL_COMMON_BLOCK_CAR
-	select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
 	select SOC_INTEL_COMMON_BLOCK_CPU
-	select SOC_INTEL_COMMON_BLOCK_DSP
-	select SOC_INTEL_COMMON_BLOCK_FAST_SPI
-	select SOC_INTEL_COMMON_BLOCK_GPIO
 	select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
 	select SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES
-	select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG
 	select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY
-	select SOC_INTEL_COMMON_BLOCK_GRAPHICS
 	select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR
-	select SOC_INTEL_COMMON_BLOCK_ITSS
-	select SOC_INTEL_COMMON_BLOCK_I2C
-	select SOC_INTEL_COMMON_BLOCK_LPC
-	select SOC_INTEL_COMMON_BLOCK_LPSS
-	select SOC_INTEL_COMMON_BLOCK_PCR
-	select SOC_INTEL_COMMON_BLOCK_P2SB
-	select SOC_INTEL_COMMON_BLOCK_PMC
+	select SOC_INTEL_COMMON_PCH_CLIENT
 	select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE
 	select SOC_INTEL_COMMON_BLOCK_SRAM
-	select SOC_INTEL_COMMON_BLOCK_RTC
 	select SOC_INTEL_COMMON_BLOCK_SA
 	select SOC_INTEL_COMMON_BLOCK_SCS
-	select SOC_INTEL_COMMON_BLOCK_TIMER
-	select SOC_INTEL_COMMON_BLOCK_TCO
-	select SOC_INTEL_COMMON_BLOCK_UART
-	select SOC_INTEL_COMMON_BLOCK_XDCI
-	select SOC_INTEL_COMMON_BLOCK_XHCI
 	select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
 	select SOC_INTEL_COMMON_BLOCK_SMM
-	select SOC_INTEL_COMMON_BLOCK_SPI
-	select SOC_INTEL_COMMON_BLOCK_CSE
-	select SOC_INTEL_COMMON_BLOCK_SMBUS
 	select SOC_INTEL_COMMON_FSP_RESET
 	select SOC_INTEL_COMMON_RESET
+	select SOC_INTEL_INTEGRATED_SOUTHCLUSTER
 	select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
 	select SOC_INTEL_NO_BOOTGUARD_MSR
-	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
 	select TSC_MONOTONIC_TIMER
 	select UDELAY_TSC
 	select UDK_2017_BINDING
@@ -277,6 +256,10 @@ config HEAP_SIZE
 	hex
 	default 0x8000
 
+config MAX_ROOT_PORTS
+	int
+	default 6
+
 config NHLT_DMIC_1CH_16B
 	bool
 	depends on ACPI_NHLT
@@ -406,4 +389,8 @@ config BOOTBLOCK_IN_CBFS
 	bool
 	default n
 
+config HAVE_PAM0_REGISTER
+	bool
+	default n
+
 endif
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index 11da0b3815..8f36d4b8e8 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -53,6 +53,7 @@ ramstage-y += graphics.c
 ramstage-y += gspi.c
 ramstage-y += heci.c
 ramstage-y += i2c.c
+ramstage-y += lockdown.c
 ramstage-y += lpc.c
 ramstage-y += mmap_boot.c
 ramstage-y += uart.c
diff --git a/src/soc/intel/apollolake/lockdown.c b/src/soc/intel/apollolake/lockdown.c
new file mode 100644
index 0000000000..1b7381da5e
--- /dev/null
+++ b/src/soc/intel/apollolake/lockdown.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <intelblocks/cfg.h>
+#include <intelblocks/pmclib.h>
+#include <intelpch/lockdown.h>
+#include <soc/pm.h>
+
+void soc_lockdown_config(int chipset_lockdown)
+{
+	/*
+	 * Nothing to do here as pmc_global_reset_disable_and_lock
+	 * is called from chip.c
+	 */
+}
diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig
index f46b95dec9..4934bb0896 100644
--- a/src/soc/intel/common/pch/Kconfig
+++ b/src/soc/intel/common/pch/Kconfig
@@ -1,3 +1,11 @@
+config SOC_INTEL_INTEGRATED_SOUTHCLUSTER
+	bool
+	help
+	  Apollo Lake and Gemini Lake are single-chip platforms with a south
+	  cluster instead of a PCH. Most of the IP blocks are the same as in
+	  PCH platforms, but there are several differences that need to be
+	  accounted for.
+
 config SOC_INTEL_COMMON_PCH_CLIENT
 	bool
 	select SOC_INTEL_COMMON_PCH_BASE
@@ -33,24 +41,27 @@ config PCH_SPECIFIC_BASE_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_FAST_SPI
 	select SOC_INTEL_COMMON_BLOCK_GPIO
 	select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG
-	select SOC_INTEL_COMMON_BLOCK_GPMR
 	select SOC_INTEL_COMMON_BLOCK_ITSS
 	select SOC_INTEL_COMMON_BLOCK_LPC
-	select SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR
 	select SOC_INTEL_COMMON_BLOCK_P2SB
 	select SOC_INTEL_COMMON_BLOCK_PCR
 	select SOC_INTEL_COMMON_BLOCK_PMC
 	select SOC_INTEL_COMMON_BLOCK_RTC
-	select SOC_INTEL_COMMON_BLOCK_SATA
 	select SOC_INTEL_COMMON_BLOCK_SMBUS
 	select SOC_INTEL_COMMON_BLOCK_SPI
 	select SOC_INTEL_COMMON_BLOCK_TCO
-	select SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS
 	select SOC_INTEL_COMMON_BLOCK_TIMER
 	select SOC_INTEL_COMMON_BLOCK_XHCI
 	select SOC_INTEL_COMMON_PCH_LOCKDOWN
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
 
+config PCH_SPECIFIC_DISCRETE_OPTIONS
+	def_bool !SOC_INTEL_INTEGRATED_SOUTHCLUSTER
+	select SOC_INTEL_COMMON_BLOCK_GPMR
+	select SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR
+	select SOC_INTEL_COMMON_BLOCK_SATA
+	select SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS
+
 config PCH_SPECIFIC_CLIENT_OPTIONS
 	def_bool SOC_INTEL_COMMON_PCH_CLIENT
 	select SOC_INTEL_COMMON_BLOCK_DSP