diff options
| author | Simon Glass <sjg@chromium.org> | 2018-07-11 15:51:27 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-07-18 20:10:45 +0000 |
| commit | e577168ae3163768bc76d23e4e121a57b436abd6 (patch) | |
| tree | 60c88848327dbf51163a4c649eeaf2409fedd8bd /src/soc | |
| parent | 82eb80cc8c08d2f676e7cb20b3b9bdf45b91d214 (diff) | |
mainboard/google/Kahlee: Select low-power mode for WiFi
Put the PCIe clock pins in power-saving mode for the WiFi module to save
power.
Note: This currently does not appear to have any effect on grunt.
BUG=b:110041917
BRANCH=none
TEST=boot without this patch:
$ iotools mem_read32 0xfed80e00
0x0046f3ff
With this patch:
$ iotools mem_read32 0xfed80e00
0x0046f3f1
Change-Id: I389815bc36b8610a30b0cbb9d73262ad392e0181
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/27465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 3127f5cd47..2e953091f8 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -366,6 +366,10 @@ #define GPP_CLK2_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK2_CLOCK_REQ_MAP_SHIFT) #define GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 3 +#define GPP_CLK0_CLOCK_REQ_MAP_SHIFT 0 +#define GPP_CLK0_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK0_CLOCK_REQ_MAP_SHIFT) +#define GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0 1 + struct stoneyridge_aoac { int enable; int status; |