soc/amd/picasso: establish full early caching memory map

The PSP does the memory training and setting up of MSRs for
TOP_MEM and TOM2. Set caching up for all the DRAM areas:

Enable WB caching for 1MiB->TOP_MEM, 4GiB->TOM2.
Enable WC caching fro 0->1MiB except 0xa0000->0xc0000.

BUG=b:155426691

Change-Id: I83916a220ea4016d4438dd4fb5be82dec5506f80
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

1 files changed, 59 insertions, 14 deletions

diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c
index 1ff689609a..606440bfc1 100644
--- a/src/soc/amd/picasso/bootblock/bootblock.c
+++ b/src/soc/amd/picasso/bootblock/bootblock.c
@@ -13,28 +13,73 @@
 #include <soc/i2c.h>
 #include <amdblocks/amd_pci_mmconf.h>
 
+/* PSP performs the memory training and setting up DRAM map prior to x86 cores
+   being released. Honor TOP_MEM and set up caching from 0 til TOP_MEM. Likewise,
+   route lower memory addresses covered by fixed MTRRs to DRAM except for
+   0xa0000-0xc0000 . */
 static void set_caching(void)
 {
-	msr_t deftype = {0, 0};
-	int mtrr;
+	msr_t top_mem;
+	msr_t sys_cfg;
+	msr_t mtrr_def_type;
+	msr_t fixed_mtrr_ram;
+	msr_t fixed_mtrr_mmio;
+	struct var_mtrr_context mtrr_ctx;
 
-	/* Disable fixed and variable MTRRs while we setup */
-	wrmsr(MTRR_DEF_TYPE_MSR, deftype);
+	var_mtrr_context_init(&mtrr_ctx, NULL);
+	top_mem = rdmsr(TOP_MEM);
+	/* Enable RdDram and WrDram attributes in fixed MTRRs. */
+	sys_cfg = rdmsr(SYSCFG_MSR);
+	sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramModEn;
+
+	/* Fixed MTRR constants. */
+	fixed_mtrr_ram.lo = fixed_mtrr_ram.hi =
+		((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) <<  0) |
+		((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) <<  8) |
+		((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 16) |
+		((MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM) << 24);
+	fixed_mtrr_mmio.lo = fixed_mtrr_mmio.hi =
+		((MTRR_TYPE_UNCACHEABLE) <<  0) |
+		((MTRR_TYPE_UNCACHEABLE) <<  8) |
+		((MTRR_TYPE_UNCACHEABLE) << 16) |
+		((MTRR_TYPE_UNCACHEABLE) << 24);
+
+	/* Prep default MTRR type. */
+	mtrr_def_type = rdmsr(MTRR_DEF_TYPE_MSR);
+	mtrr_def_type.lo &= ~MTRR_DEF_TYPE_MASK;
+	mtrr_def_type.lo |= MTRR_TYPE_UNCACHEABLE;
+	mtrr_def_type.lo |= MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN;
+
+	disable_cache();
+
+	wrmsr(SYSCFG_MSR, sys_cfg);
 
 	clear_all_var_mtrr();
 
-	mtrr = get_free_var_mtrr();
-	if (mtrr >= 0)
-		set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
+	var_mtrr_set(&mtrr_ctx, 0, ALIGN_DOWN(top_mem.lo, 8*MiB), MTRR_TYPE_WRBACK);
+	var_mtrr_set(&mtrr_ctx, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
+
+	/* Set up RAM caching for everything below 1MiB except for 0xa0000-0xc0000 . */
+	wrmsr(MTRR_FIX_64K_00000, fixed_mtrr_ram);
+	wrmsr(MTRR_FIX_16K_80000, fixed_mtrr_ram);
+	wrmsr(MTRR_FIX_16K_A0000, fixed_mtrr_mmio);
+	wrmsr(MTRR_FIX_4K_C0000, fixed_mtrr_ram);
+	wrmsr(MTRR_FIX_4K_C8000, fixed_mtrr_ram);
+	wrmsr(MTRR_FIX_4K_D0000, fixed_mtrr_ram);
+	wrmsr(MTRR_FIX_4K_D8000, fixed_mtrr_ram);
+	wrmsr(MTRR_FIX_4K_E0000, fixed_mtrr_ram);
+	wrmsr(MTRR_FIX_4K_E8000, fixed_mtrr_ram);
+	wrmsr(MTRR_FIX_4K_F0000, fixed_mtrr_ram);
+	wrmsr(MTRR_FIX_4K_F8000, fixed_mtrr_ram);
 
-	mtrr = get_free_var_mtrr();
-	if (mtrr >= 0)
-		set_var_mtrr(mtrr, (unsigned int)_bootblock, REGION_SIZE(bootblock),
-			     MTRR_TYPE_WRBACK);
+	wrmsr(MTRR_DEF_TYPE_MSR, mtrr_def_type);
 
-	/* Enable variable MTRRs. Fixed MTRRs are left disabled since they are not used. */
-	deftype.lo |= MTRR_DEF_TYPE_EN | MTRR_TYPE_UNCACHEABLE;
-	wrmsr(MTRR_DEF_TYPE_MSR, deftype);
+	/* Enable Fixed and Variable MTRRs. */
+	sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn;
+	sys_cfg.lo |= SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB;
+	/* AGESA currently expects SYSCFG_MSR_MtrrFixDramModEn to be set. Once
+	   MP init happens in coreboot proper it can be knocked down. */
+	wrmsr(SYSCFG_MSR, sys_cfg);
 
 	enable_cache();
 }