storm: Initialize clock, pinmux for NAND if present on board

This patch runs basic NAND initialization code on Proto 0.2 boards which
have been reworked for NAND. It makes sense to do this in coreboot for
two reasons:
- In general, it is reasonable for coreboot to initialize clocks and such
  in preparation for depthcharge's use. Waiting times can be pooled, and
  the initialization itself here is very fast.
- There is a kernel bug which requires that the clock is already initialized
  before the kernel loads NAND support. coreboot is a more sensible place
  to put a workaround than depthcharge because depthcharge initializes
  things lazily, but when booting from USB, depthcharge won't need to look
  at NAND.
This change involves bringing in an additional header file, ebi2.h, from U-Boot.

TEST=Booted a kernel from USB and verified that NAND came up without any
depthcharge hacks, whereas previously a USB-booted kernel would be unable
to access NAND even with the same drivers compiled in due to an initialization
failure.
BUG=chromium:403432
BRANCH=none

Change-Id: I04e99cb39d16848a6ed75fe0229b8f79bdf2e035
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9be29da5ccad9982f146ae00344f30598ef2371c
Original-Signed-off-by: Dan Ehrenberg <dehrenberg@chromium.org>
Original-Change-Id: I1760ecb4e47438311d80e34326e45578c608481c
Original-Reviewed-on: https://chromium-review.googlesource.com/225277
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9402
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

2 files changed, 92 insertions, 1 deletions

diff --git a/src/soc/qualcomm/ipq806x/include/soc/cdp.h b/src/soc/qualcomm/ipq806x/include/soc/cdp.h
index c7de23f4e8..bb2151cd2d 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/cdp.h
+++ b/src/soc/qualcomm/ipq806x/include/soc/cdp.h
@@ -106,6 +106,12 @@ typedef struct {
 
 #define IPQ_GMAC_NMACS		4
 
+enum storm_board_id {
+	BOARD_ID_PROTO_0 = 0,
+	BOARD_ID_PROTO_0_2 = 1,
+	BOARD_ID_PROTO_0_2_NAND = 26,
+};
+
 /* Board specific parameters */
 typedef struct {
 #if 0
@@ -136,4 +142,7 @@ static inline int gmac_cfg_is_valid(ipq_gmac_board_cfg_t *cfg)
 
 unsigned int get_board_index(unsigned machid);
 void ipq_configure_gpio(const gpio_func_data_t *gpio, unsigned count);
-#endif
+
+void board_nand_init(void);
+
+#endif	/* _IPQ806X_CDP_H_ */
diff --git a/src/soc/qualcomm/ipq806x/include/soc/ebi2.h b/src/soc/qualcomm/ipq806x/include/soc/ebi2.h
new file mode 100644
index 0000000000..770ac1093d
--- /dev/null
+++ b/src/soc/qualcomm/ipq806x/include/soc/ebi2.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2012 The Linux Foundation. All rights reserved.
+ *
+ * Taken from U-Boot.
+ */
+#ifndef __SOC_QUALCOMM_IPQ806X_EBI2_H_
+#define __SOC_QUALCOMM_IPQ806X_EBI2_H_
+
+#define EBI2CR_BASE                                       (0x1A600000)
+
+struct ebi2cr_regs {
+	uint32_t chip_select_cfg0;                        /* 0x00000000 */
+	uint32_t cfg;                                     /* 0x00000004 */
+	uint32_t hw_info;                                 /* 0x00000008 */
+	uint8_t reserved0[20];
+	uint32_t lcd_cfg0;                                /* 0x00000020 */
+	uint32_t lcd_cfg1;                                /* 0x00000024 */
+	uint8_t reserved1[8];
+	uint32_t arbiter_cfg;                             /* 0x00000030 */
+	uint8_t reserved2[28];
+	uint32_t debug_sel;                               /* 0x00000050 */
+	uint32_t crc_cfg;                                 /* 0x00000054 */
+	uint32_t crc_reminder_cfg;                        /* 0x00000058 */
+	uint32_t nand_adm_mux;                            /* 0x0000005C */
+	uint32_t mutex_addr_offset;                       /* 0x00000060 */
+	uint32_t misr_value;                              /* 0x00000064 */
+	uint32_t clkon_cfg;                               /* 0x00000068 */
+	uint32_t core_clkon_cfg;                          /* 0x0000006C */
+};
+
+/* Register: EBI2_CHIP_SELECT_CFG0 */
+#define CS7_CFG_MASK                             0x00001000
+#define CS7_CFG_DISABLE                          0x00000000
+#define CS7_CFG_GENERAL_SRAM_MEMORY_INTERFACE    0x00001000
+#define CS7_CFG(i)                               ((i) << 12)
+
+#define CS6_CFG_MASK                             0x00000800
+#define CS6_CFG_DISABLE                          0x00000000
+#define CS6_CFG_GENERAL_SRAM_MEMORY_INTERFACE    0x00000800
+#define CS6_CFG(i)                               ((i) << 11)
+
+#define ETM_CS_CFG_MASK                          0x00000400
+#define ETM_CS_CFG_DISABLE                       0x00000000
+#define ETM_CS_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000400
+#define ETM_CS_CFG(i)                            ((i) << 10)
+
+#define CS5_CFG_MASK                             0x00000300
+#define CS5_CFG_DISABLE                          0x00000000
+#define CS5_CFG_LCD_DEVICE_CONNECTED             0x00000100
+#define CS5_CFG_LCD_DEVICE_CHIP_ENABLE           0x00000200
+#define CS5_CFG_GENERAL_SRAM_MEMORY_INTERFACE    0x00000300
+#define CS5_CFG(i)                               ((i) << 8)
+
+#define CS4_CFG_MASK                             0x000000c0
+#define CS4_CFG_DISABLE                          0x00000000
+#define CS4_CFG_LCD_DEVICE_CONNECTED             0x00000040
+#define CS4_CFG_GENERAL_SRAM_MEMORY_INTERFACE    0x000000C0
+#define CS4_CFG(i)                               ((i) << 6)
+
+#define CS3_CFG_MASK                             0x00000020
+#define CS3_CFG_DISABLE                          0x00000000
+#define CS3_CFG_GENERAL_SRAM_MEMORY_INTERFACE    0x00000020
+#define CS3_CFG(i)                               ((i) << 5)
+
+#define CS2_CFG_MASK                             0x00000010
+#define CS2_CFG_DISABLE                          0x00000000
+#define CS2_CFG_GENERAL_SRAM_MEMORY_INTERFACE    0x00000010
+#define CS2_CFG(i)                               ((i) << 4)
+
+#define CS1_CFG_MASK                             0x0000000c
+#define CS1_CFG_DISABLE                          0x00000000
+#define CS1_CFG_SERIAL_FLASH_DEVICE              0x00000004
+#define CS1_CFG_GENERAL_SRAM_MEMORY_INTERFACE    0x00000008
+#define CS1_CFG(i)                               ((i) << 2)
+
+#define CS0_CFG_MASK                             0x00000003
+#define CS0_CFG_DISABLE                          0x00000000
+#define CS0_CFG_SERIAL_FLASH_DEVICE              0x00000001
+#define CS0_CFG_GENERAL_SRAM_MEMORY_INTERFACE    0x00000002
+#define CS0_CFG(i)                               ((i) << 0)
+
+#endif