diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-02-02 16:15:17 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-03 19:59:54 +0000 |
| commit | 70f1af8934db9ca840eff994f93ae3aaa096bf84 (patch) | |
| tree | a6a911b58ff2d973a305288ea86cfee6198080cf /src/soc | |
| parent | 4c4a360018315b3bd60d3cfc3506137a631ee7ba (diff) | |
soc/amd/cezanne: remove UART2/3 AOAC device offsets
UART2 and UART3 don't exist on Cezanne which now has been verified, so
remove the corresponding AOAC offsets.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I67755bd34df3a835cc39929bdc24f711d158b3a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/southbridge.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 6949fa57b3..a38d706f23 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -22,9 +22,7 @@ #define FCH_AOAC_DEV_I2C5 10 #define FCH_AOAC_DEV_UART0 11 #define FCH_AOAC_DEV_UART1 12 -#define FCH_AOAC_DEV_UART2 16 #define FCH_AOAC_DEV_AMBA 17 -#define FCH_AOAC_DEV_UART3 26 #define FCH_AOAC_DEV_ESPI 27 /* IO 0xf0 NCP Error */ |