diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2016-10-25 20:05:31 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2016-10-27 16:30:13 +0200 |
| commit | 64ce1d122c0464a4ef138fb7452a91b408b1a7c2 (patch) | |
| tree | dc7c3d0d3618f501670515fb9746f8a3c7131c0b /src/soc | |
| parent | 95f9020de162f29b8b30af361339c94c298acf52 (diff) | |
skylake: Support for early I2C TPM driver
Add the SOC definition for acpi_get_gpe() so it can be used
by the I2C TPM driver. Also add the I2C support code to
verstage so it can get used by vboot.
BUG=chrome-os-partner:58666
TEST=boot with I2C TPM on skylake board
Change-Id: I553f00a6ec25955ecc18a7616d9c3e1e7cbbb8ca
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17136
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/skylake/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/soc/intel/skylake/pmutil.c | 20 |
2 files changed, 22 insertions, 1 deletions
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index bf429ef902..1714572f0a 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -30,7 +30,8 @@ bootblock-y += tsc_freq.c verstage-y += flash_controller.c verstage-y += monotonic_timer.c verstage-y += pch.c -verstage-$(CONFIG_UART_DEBUG) += uart_debug.c +verstage-y += pmutil.c +verstage-y += bootblock/i2c.c romstage-y += flash_controller.c romstage-y += gpio.c diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 31de242752..904be5c2a0 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -351,6 +351,26 @@ u32 clear_gpe_status(void) gpe0_sts_3_bits); } +/* Read and clear GPE status (defined in arch/acpi.h) */ +int acpi_get_gpe(int gpe) +{ + int bank; + uint32_t mask, sts; + + if (gpe < 0 || gpe > GPE0_WADT) + return -1; + + bank = gpe / 32; + mask = 1 << (gpe % 32); + + sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(bank)); + if (sts & mask) { + outl(mask, ACPI_BASE_ADDRESS + GPE0_STS(bank)); + return 1; + } + return 0; +} + /* Enable all requested GPE */ void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4) { |