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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-05-23 15:24:30 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-04 11:25:32 +0000 |
| commit | 59b6542bbc5aa7215aa68eca098c047924e5e118 (patch) | |
| tree | a4e0e0c652cb0b4a633e42818f4310bb2f889bcc /src/soc | |
| parent | 0e9116f0a12c0a2a8142978458d3266e5e9aacdc (diff) | |
soc/intel/braswell: Use common cpu/intel/car code
The code in cpu/intel/car/romstage.c Does most of the things like
setting up timestamps, stack guards, entering postcar.
A functional difference is that the FSP header is searched for twice
instead of passed from the CAR entry to the C code. When using
C_ENVIRONMENT_BOOTBLOCK this needs to be done anyway (or a special
linker symbol kept across multiple stages is needed, which is likely
not worth the speedup).
Change-Id: I0f03e5a808f00157fdd807b104417a54e4bde7b2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/braswell/romstage/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/romstage/Makefile.inc b/src/soc/intel/braswell/romstage/Makefile.inc index 15de822041..3d3e407a29 100644 --- a/src/soc/intel/braswell/romstage/Makefile.inc +++ b/src/soc/intel/braswell/romstage/Makefile.inc @@ -1,2 +1,3 @@ +romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += pmc.c romstage-y += romstage.c |