summaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
authorHannah Williams <hannah.williams@intel.com>2016-01-28 14:25:32 -0800
committerPatrick Georgi <pgeorgi@google.com>2016-01-29 16:58:19 +0100
commit5166827c57a95eb1e86e20799fe4e511e0eda8d7 (patch)
treedf9fe1e99d559974a2cf6201e583671896637c27 /src/soc
parent3e3d969e6f4d851faed0dccf73c16440a56f9c13 (diff)
soc/braswell: Fix Global NVS base address
TEST=Boot to OS Signed-off-by: Hannah Williams <hannah.williams@intel.com> Change-Id: I9b43eb4f6f7af62a8a0bbe7bfa08feee1eaca24e Reviewed-on: https://review.coreboot.org/13506 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/braswell/acpi/globalnvs.asl3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl
index 5c8a75fcb9..a53834a254 100644
--- a/src/soc/intel/braswell/acpi/globalnvs.asl
+++ b/src/soc/intel/braswell/acpi/globalnvs.asl
@@ -25,8 +25,9 @@ Name(\PICM, 0) /* IOAPIC/8259 */
* we have to fix it up in coreboot's ACPI creation phase.
*/
+External (NVSA)
-OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0x2000)
+OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */