lib/cbmem_top: Add a common cbmem_top implementation

This adds a common cbmem_top implementation to all coreboot target.

In romstage a static variable will be used to cache the result of
cbmem_top_romstage.

In ramstage if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is set a global variable
needs to be populated by the stage entry with the value passed via the
calling arguments. if CONFIG_RAMSTAGE_CBMEM_TOP_ARG is not set the
same implementation as will be used as in romstage.

Change-Id: Ie767542ee25483acc9a56785ce20a885e9a63098
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

28 files changed, 28 insertions, 28 deletions

diff --git a/src/soc/amd/picasso/memmap.c b/src/soc/amd/picasso/memmap.c
index 09af7e4de7..82d6fb6e8e 100644
--- a/src/soc/amd/picasso/memmap.c
+++ b/src/soc/amd/picasso/memmap.c
@@ -58,7 +58,7 @@ void bert_reserved_region(void **start, size_t *size)
 	*size = BERT_REGION_MAX_SIZE;
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	msr_t tom = rdmsr(TOP_MEM);
 
diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c
index 09af7e4de7..82d6fb6e8e 100644
--- a/src/soc/amd/stoneyridge/memmap.c
+++ b/src/soc/amd/stoneyridge/memmap.c
@@ -58,7 +58,7 @@ void bert_reserved_region(void **start, size_t *size)
 	*size = BERT_REGION_MAX_SIZE;
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	msr_t tom = rdmsr(TOP_MEM);
 
diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c
index bb6fa18f20..a39bf4fe35 100644
--- a/src/soc/cavium/cn81xx/cbmem.c
+++ b/src/soc/cavium/cn81xx/cbmem.c
@@ -20,7 +20,7 @@
 #include <stdlib.h>
 #include <symbols.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	/* Make sure not to overlap with reserved ATF scratchpad */
 	return (void *)((uintptr_t)_dram + (sdram_size_mb() - 1) * MiB);
diff --git a/src/soc/imgtec/pistachio/cbmem.c b/src/soc/imgtec/pistachio/cbmem.c
index 112df7ccc9..92bc1ce868 100644
--- a/src/soc/imgtec/pistachio/cbmem.c
+++ b/src/soc/imgtec/pistachio/cbmem.c
@@ -18,7 +18,7 @@
 #include <stdlib.h>
 #include <symbols.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return _dram + (CONFIG_DRAM_SIZE_MB << 20);
 }
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c
index f828024d29..567ff1ebc6 100644
--- a/src/soc/intel/apollolake/memmap.c
+++ b/src/soc/intel/apollolake/memmap.c
@@ -20,7 +20,7 @@
 
 #include "chip.h"
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	const config_t *config;
 	void *tolum = (void *)sa_get_tseg_base();
diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c
index d9f6160dfc..e0aac9f423 100644
--- a/src/soc/intel/baytrail/memmap.c
+++ b/src/soc/intel/baytrail/memmap.c
@@ -29,7 +29,7 @@ static size_t smm_region_size(void)
 	return CONFIG_SMM_TSEG_SIZE;
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *) smm_region_start();
 }
diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c
index d502aed9f9..e43c5469f6 100644
--- a/src/soc/intel/braswell/memmap.c
+++ b/src/soc/intel/braswell/memmap.c
@@ -33,7 +33,7 @@ void smm_region(uintptr_t *start, size_t *size)
 	*size = smm_region_size();
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	uintptr_t smm_base;
 	size_t smm_size;
diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c
index f4a9d0ed24..ad50dd35db 100644
--- a/src/soc/intel/broadwell/memmap.c
+++ b/src/soc/intel/broadwell/memmap.c
@@ -41,7 +41,7 @@ static uintptr_t dpr_region_start(void)
 	return tom;
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *) dpr_region_start();
 }
diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c
index 475b8c79db..7a0d89717b 100644
--- a/src/soc/intel/cannonlake/memmap.c
+++ b/src/soc/intel/cannonlake/memmap.c
@@ -247,7 +247,7 @@ void cbmem_top_init(void)
  *     |                         |
  *     +-------------------------+
  */
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	struct ebda_config ebda_cfg;
 
diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c
index 9f788ddb41..b4761dbeef 100644
--- a/src/soc/intel/denverton_ns/memmap.c
+++ b/src/soc/intel/denverton_ns/memmap.c
@@ -60,7 +60,7 @@ u32 top_of_32bit_ram(void)
 	       power_of_2(iqat_region_size + tseg_region_size);
 }
 
-void *cbmem_top(void) { return (void *)top_of_32bit_ram(); }
+void *cbmem_top_chipset(void) { return (void *)top_of_32bit_ram(); }
 
 static inline uintptr_t smm_region_start(void)
 {
diff --git a/src/soc/intel/fsp_baytrail/memmap.c b/src/soc/intel/fsp_baytrail/memmap.c
index 7fec7f9764..d8dcf49acb 100644
--- a/src/soc/intel/fsp_baytrail/memmap.c
+++ b/src/soc/intel/fsp_baytrail/memmap.c
@@ -40,7 +40,7 @@ static size_t smm_region_size(void)
  * @return pointer to the first byte of reserved memory
  */
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR);
 }
diff --git a/src/soc/intel/fsp_broadwell_de/memmap.c b/src/soc/intel/fsp_broadwell_de/memmap.c
index cbd3cf7788..96eb20502c 100644
--- a/src/soc/intel/fsp_broadwell_de/memmap.c
+++ b/src/soc/intel/fsp_broadwell_de/memmap.c
@@ -23,7 +23,7 @@
 #include <soc/pci_devs.h>
 #include <device/pci_ops.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return find_fsp_reserved_mem(*(void **)CBMEM_FSP_HOB_PTR);
 }
diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c
index f17f255b13..76a8128520 100644
--- a/src/soc/intel/icelake/memmap.c
+++ b/src/soc/intel/icelake/memmap.c
@@ -226,7 +226,7 @@ void cbmem_top_init(void)
  *     |                         |
  *     +-------------------------+
  */
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	struct ebda_config ebda_cfg;
 
diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c
index b8b85063a8..9ccaf55a1f 100644
--- a/src/soc/intel/quark/memmap.c
+++ b/src/soc/intel/quark/memmap.c
@@ -18,7 +18,7 @@
 #include <cbmem.h>
 #include <soc/reg_access.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	uint32_t top_of_memory;
 
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index 3aea1c31e6..09dc6e9f0d 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -248,7 +248,7 @@ void cbmem_top_init(void)
  *     |                         |
  *     +-------------------------+
  */
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	struct ebda_config ebda_cfg;
 
diff --git a/src/soc/mediatek/common/cbmem.c b/src/soc/mediatek/common/cbmem.c
index 8906565bd5..1a55d0113e 100644
--- a/src/soc/mediatek/common/cbmem.c
+++ b/src/soc/mediatek/common/cbmem.c
@@ -21,7 +21,7 @@
 
 #define MAX_DRAM_ADDRESS ((uintptr_t)4 * GiB)
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *)min((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS);
 }
diff --git a/src/soc/nvidia/tegra124/cbmem.c b/src/soc/nvidia/tegra124/cbmem.c
index 4b52a519bd..ac2a92e39d 100644
--- a/src/soc/nvidia/tegra124/cbmem.c
+++ b/src/soc/nvidia/tegra124/cbmem.c
@@ -17,7 +17,7 @@
 #include <soc/display.h>
 #include <soc/sdram.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *)((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL);
 }
diff --git a/src/soc/nvidia/tegra210/cbmem.c b/src/soc/nvidia/tegra210/cbmem.c
index 63ae497ebb..7fdde9e6ea 100644
--- a/src/soc/nvidia/tegra210/cbmem.c
+++ b/src/soc/nvidia/tegra210/cbmem.c
@@ -16,7 +16,7 @@
 #include <cbmem.h>
 #include <soc/addressmap.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	static uintptr_t addr;
 
diff --git a/src/soc/qualcomm/ipq40xx/cbmem.c b/src/soc/qualcomm/ipq40xx/cbmem.c
index 05325cceb9..972c6258c9 100644
--- a/src/soc/qualcomm/ipq40xx/cbmem.c
+++ b/src/soc/qualcomm/ipq40xx/cbmem.c
@@ -23,7 +23,7 @@ void ipq_cbmem_backing_store_ready(void)
 	cbmem_backing_store_ready = 1;
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	/*
 	 * In romstage, make sure that cbmem backing store is ready before
diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c
index 9674db65da..6dc92a0c11 100644
--- a/src/soc/qualcomm/ipq806x/cbmem.c
+++ b/src/soc/qualcomm/ipq806x/cbmem.c
@@ -23,7 +23,7 @@ void ipq_cbmem_backing_store_ready(void)
 	cbmem_backing_store_ready = 1;
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	/*
 	 * In romstage, make sure that cbmem backing store is ready before
diff --git a/src/soc/qualcomm/qcs405/cbmem.c b/src/soc/qualcomm/qcs405/cbmem.c
index e065409622..a780c6bcf1 100644
--- a/src/soc/qualcomm/qcs405/cbmem.c
+++ b/src/soc/qualcomm/qcs405/cbmem.c
@@ -15,7 +15,7 @@
 
 #include <cbmem.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *)((uintptr_t)3 * GiB);
 }
diff --git a/src/soc/qualcomm/sc7180/cbmem.c b/src/soc/qualcomm/sc7180/cbmem.c
index 597e3692f8..fe81309c7a 100644
--- a/src/soc/qualcomm/sc7180/cbmem.c
+++ b/src/soc/qualcomm/sc7180/cbmem.c
@@ -15,7 +15,7 @@
 
 #include <cbmem.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *)((uintptr_t)4 * GiB);
 }
diff --git a/src/soc/qualcomm/sdm845/cbmem.c b/src/soc/qualcomm/sdm845/cbmem.c
index 3b9ad4a617..b092a1a610 100644
--- a/src/soc/qualcomm/sdm845/cbmem.c
+++ b/src/soc/qualcomm/sdm845/cbmem.c
@@ -15,7 +15,7 @@
 
 #include <cbmem.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *)((uintptr_t)4 * GiB);
 }
diff --git a/src/soc/rockchip/common/cbmem.c b/src/soc/rockchip/common/cbmem.c
index 401f8b2a65..6e3aabb81c 100644
--- a/src/soc/rockchip/common/cbmem.c
+++ b/src/soc/rockchip/common/cbmem.c
@@ -19,7 +19,7 @@
 #include <stdlib.h>
 #include <symbols.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB,
 			   MAX_DRAM_ADDRESS);
diff --git a/src/soc/samsung/exynos5250/cbmem.c b/src/soc/samsung/exynos5250/cbmem.c
index 1874495396..31463b19b5 100644
--- a/src/soc/samsung/exynos5250/cbmem.c
+++ b/src/soc/samsung/exynos5250/cbmem.c
@@ -17,7 +17,7 @@
 #include <cbmem.h>
 #include <soc/cpu.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *)(get_fb_base_kb() * KiB);
 }
diff --git a/src/soc/samsung/exynos5420/cbmem.c b/src/soc/samsung/exynos5420/cbmem.c
index e1999e888e..ffed589ee1 100644
--- a/src/soc/samsung/exynos5420/cbmem.c
+++ b/src/soc/samsung/exynos5420/cbmem.c
@@ -17,7 +17,7 @@
 #include <soc/cpu.h>
 #include <stddef.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *)(get_fb_base_kb() * KiB);
 }
diff --git a/src/soc/sifive/fu540/cbmem.c b/src/soc/sifive/fu540/cbmem.c
index 1c68de894b..a7de16c56a 100644
--- a/src/soc/sifive/fu540/cbmem.c
+++ b/src/soc/sifive/fu540/cbmem.c
@@ -19,7 +19,7 @@
 #include <stdlib.h>
 #include <symbols.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *)min((uintptr_t)_dram + sdram_size_mb() * MiB,
 			   FU540_MAXDRAM);
diff --git a/src/soc/ucb/riscv/cbmem.c b/src/soc/ucb/riscv/cbmem.c
index 542e08d05e..143e11b88c 100644
--- a/src/soc/ucb/riscv/cbmem.c
+++ b/src/soc/ucb/riscv/cbmem.c
@@ -15,7 +15,7 @@
 #include <symbols.h>
 #include <ramdetect.h>
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return _dram + (probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB) * MiB);
 }