diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2017-08-26 04:53:35 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-09-08 21:09:19 +0000 |
| commit | 2c8ac228739373f6f03c70ffcc263bd23ba01ac6 (patch) | |
| tree | bfe4b2d1b6ea9713eb9db5f7593a2a0b9bcd3bb4 /src/soc | |
| parent | 143a836e5a9708de77133d99aa5719780c3f9596 (diff) | |
soc/intel/braswell: Add USB2 phy setting override
Adapted from Chromium commit 9756af8.
Create hook function to override USB2 phy setting from board level.
Original-Change-Id: Ic736dd945f01cf9f24af4ce3bd3f2757abfdeb2e
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
Change-Id: If2ac687f6fc44e4c022a72eea7f08cb6385f0380
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/braswell/chip.c | 5 | ||||
| -rw-r--r-- | src/soc/intel/braswell/include/soc/ramstage.h | 1 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index e0c1a511d3..afa90c32db 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -81,6 +81,10 @@ static void enable_dev(device_t dev) } } +__attribute__((weak)) void board_silicon_USB2_override(SILICON_INIT_UPD *params) +{ +} + void soc_silicon_init_params(SILICON_INIT_UPD *params) { device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); @@ -170,6 +174,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) params->I2C5Frequency = config->I2C5Frequency; params->I2C6Frequency = config->I2C6Frequency; + board_silicon_USB2_override(params); } void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, diff --git a/src/soc/intel/braswell/include/soc/ramstage.h b/src/soc/intel/braswell/include/soc/ramstage.h index e67cc3b2f6..3f8249bbbb 100644 --- a/src/soc/intel/braswell/include/soc/ramstage.h +++ b/src/soc/intel/braswell/include/soc/ramstage.h @@ -101,6 +101,7 @@ void set_max_freq(void); void southcluster_enable_dev(device_t dev); void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index); int SocStepping(void); +void board_silicon_USB2_override(SILICON_INIT_UPD *params); extern struct pci_operations soc_pci_ops; |