diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-06-04 14:12:01 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-11-10 22:40:59 +0000 |
| commit | 2abbe467658a8e4479c381330e85e126c8f42a90 (patch) | |
| tree | 814bb1a711c25c03e9b502520336bfdd98cad2df /src/soc | |
| parent | 1d4bdda47f030d01418936d3399856dddfa7f43b (diff) | |
soc/intel/broadwell: Use common SB RTC code
Change-Id: Iedb9a8962ac1b4107e9192b0be610fb92d2cfdc6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/broadwell/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/include/soc/pm.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/lpc.c | 8 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/pmutil.c | 26 |
4 files changed, 3 insertions, 35 deletions
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 0bbb668c98..f69c7de4a7 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_RESET + select SOUTHBRIDGE_INTEL_COMMON_RTC select HAVE_USBDEBUG select IOAPIC select REG_SCRIPT diff --git a/src/soc/intel/broadwell/include/soc/pm.h b/src/soc/intel/broadwell/include/soc/pm.h index 343cf2ba68..18004fa77d 100644 --- a/src/soc/intel/broadwell/include/soc/pm.h +++ b/src/soc/intel/broadwell/include/soc/pm.h @@ -155,7 +155,4 @@ void disable_gpe(uint32_t mask); /* Return the selected ACPI SCI IRQ */ int acpi_sci_irq(void); -/* Return non-zero when RTC failure happened. */ -int rtc_failure(void); - #endif diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 873f594530..3392614303 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -42,6 +42,7 @@ #include <soc/rcba.h> #include <soc/intel/broadwell/chip.h> #include <arch/acpigen.h> +#include <southbridge/intel/common/rtc.h> static void pch_enable_ioapic(struct device *dev) { @@ -190,11 +191,6 @@ static void pch_power_options(struct device *dev) enable_alt_smi(config->alt_gp_smi_en); } -static void pch_rtc_init(struct device *dev) -{ - cmos_init(rtc_failure()); -} - static const struct reg_script pch_misc_init_script[] = { /* Setup SLP signal assertion, SLP_S4=4s, SLP_S3=50ms */ REG_PCI_RMW16(GEN_PMCON_3, ~((3 << 4)|(1 << 10)), @@ -439,7 +435,7 @@ static void lpc_init(struct device *dev) { /* Legacy initialization */ isa_dma_init(); - pch_rtc_init(dev); + sb_rtc_init(); reg_script_run_on_dev(dev, pch_misc_init_script); /* Interrupt configuration */ diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c index 322e96f4a0..00db6156ec 100644 --- a/src/soc/intel/broadwell/pmutil.c +++ b/src/soc/intel/broadwell/pmutil.c @@ -451,32 +451,6 @@ int acpi_sci_irq(void) return sci_irq; } -int rtc_failure(void) -{ - u8 reg8; - int rtc_failed; -#if defined(__SIMPLE_DEVICE__) - pci_devfn_t dev = PCH_DEV_LPC; -#else - struct device *dev = PCH_DEV_LPC; -#endif - - reg8 = pci_read_config8(dev, GEN_PMCON_3); - rtc_failed = reg8 & RTC_BATTERY_DEAD; - if (rtc_failed) { - reg8 &= ~RTC_BATTERY_DEAD; - pci_write_config8(dev, GEN_PMCON_3, reg8); - printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); - } - - return !!rtc_failed; -} - -int vbnv_cmos_failed(void) -{ - return rtc_failure(); -} - int vboot_platform_is_resuming(void) { if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) |