diff options
| author | Aamir Bohra <aamir.bohra@intel.com> | 2019-05-17 12:31:51 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2019-06-12 22:48:36 +0000 |
| commit | 2973d1e4783a24246292b58b3e9b7ee6aef1222d (patch) | |
| tree | a6d25ffbafa95a2048942d00535b4fc0dddd4031 /src/soc | |
| parent | 702d2364bd6aef6871201fc324534c2695e1a632 (diff) | |
vendorcode/intel/fsp/fsp2_0/cometlake: Update FSP-M/S header files as per v1155
This CL implements below changes:
1) Update FSP-M and FSP-S header files as per FSP release version 1155.
2) Update the PcdSerialIoUartNumber reference in fsp_params.c with
SerialIoUartDebugControllerNumber.
Change-Id: I6d412424f9f5c5d2d56b789c2fef4bdb817a3019
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32844
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/cannonlake/romstage/fsp_params.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 6e492bb73a..77bad8f627 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -50,7 +50,11 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) m_cfg->PcieRpEnableMask = mask; m_cfg->PrmrrSize = config->PrmrrSize; m_cfg->EnableC6Dram = config->enable_c6dram; +#if CONFIG(SOC_INTEL_COMETLAKE) + m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; +#else m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE; +#endif /* * PcdDebugInterfaceFlags * This config will allow coreboot to pass information to the FSP |