diff options
| author | Duncan Laurie <dlaurie@google.com> | 2018-09-13 16:28:13 +0000 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-09-28 09:56:02 +0000 |
| commit | 174ca43583f33400094fb40c1e689a38946bdeac (patch) | |
| tree | 4d2bfab50060ca5384bee1a44ad50bffee5faa47 /src/soc | |
| parent | 0c392b3cfc0e1bb04fe1fefc234ce23b13e50306 (diff) | |
soc/intel/cannonlake: Fix ACPI FADT table generation
The function to fill out the FADT table exits early if the devicetree
config option to disable the legacy timer is set. This means it never
gets to the later check for s0ix config option and so the flag to
indicate that it supports low-power idle in S0 is not set.
Change-Id: Ia0416f21b6445f6feecb6f0301d48fdf2522b8a6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/28755
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/cannonlake/acpi.c | 25 |
1 files changed, 12 insertions, 13 deletions
diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 155756c02c..a27055a118 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -176,19 +176,18 @@ void soc_fill_fadt(acpi_fadt_t *fadt) const struct device *dev = PCH_DEV_LPC; const struct soc_intel_cannonlake_config *config = dev->chip_info; - if (config->PmTimerDisabled != 0) - return; - - fadt->pm_tmr_blk = pmbase + PM1_TMR; - fadt->pm_tmr_len = 4; - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; - fadt->x_pm_tmr_blk.addrh = 0x0; - - if(config->s0ix_enable) + if (!config->PmTimerDisabled) { + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->pm_tmr_len = 4; + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + fadt->x_pm_tmr_blk.addrh = 0x0; + } + + if (config->s0ix_enable) fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; } uint32_t soc_read_sci_irq_select(void) |