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authorVaradarajan Narayanan <varada@codeaurora.org>2016-03-17 14:37:56 +0530
committerPatrick Georgi <pgeorgi@google.com>2016-05-10 21:42:52 +0200
commit10c37492076fdfcdb778bd1e5ddf327cf5f814f5 (patch)
tree8e7eb18b49dc4ac90e9bbf98f729cec866b6e207 /src/soc
parent2817cc568c9703c379a66f01a4ae5cc95e98013d (diff)
soc/qualcomm/ipq40xx: Update memory map to align to ipq40xx
Update the memory to map to align with the internal memory region map of IPQ40XX BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: e33712a729ef9831508c2e9aae81d0b32495b681 Original-Change-Id: Iba1c5281a2fbda4ab96126676b901ba71f6b28e0 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333295 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> squashed: soc/qualcomm/ipq40xx: Update DRAM address ranges BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: 9150c125cb82f8dccb1347d898106703d85a5192 Original-Change-Id: Ic48d3e3f46a7c13a009a5cbed20984bd253eb85b Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333296 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Change-Id: Iea40484751a1c0439ed511319ef09a0254eba757 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14654 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld67
1 files changed, 40 insertions, 27 deletions
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld
index 6ff2b77608..de8488ac53 100644
--- a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld
+++ b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld
@@ -18,34 +18,47 @@
#include <arch/header.ld>
+#define REGION_START(name, addr) SYMBOL(name, addr)
+#define REGION_END(name, addr) SYMBOL(e##name, addr)
+
SECTIONS
{
- REGION(rpm, 0x00020000, 160K, 8K)
- SRAM_START(0x2A000000)
+ REGION(oc_imem, 0x08600000, 32K, 0)
+
+ /* ==vvv== OC_IMEM_1_START 0x08600000 ==vvv== */
+/* DDR(0x08600000, 32K) */
+ /* ==^^^== OC_IMEM_1_END 0x08608000 ==^^^== */
+
+ /* ==vvv== WIFI_IMEM_0_START 0x0A0C0000 ==vvv== */
+ REGION_START(wifi_imem_0, 0x0A0C0000)
/* This includes bootblock image, can be reused after bootblock starts */
-/* UBER_SBL(0x2A000000, 48K) */
-/* DDR(0x2A000000, 48K) */
- BOOTBLOCK(0x2A00C000, 24K)
- OVERLAP_VERSTAGE_ROMSTAGE(0x2A012000, 64K)
- VBOOT2_WORK(0x2A022000, 16K)
- PRERAM_CBMEM_CONSOLE(0x2A026000, 32K)
- TIMESTAMP(0x2A02E000, 1K)
-
-/* 0x2e400..0x3F000 67 KB free */
-
-/* Keep the below area reserved at all times, it is used by various QCA
- components as shared data
- QCA_SHARED_RAM(2A03F000, 4K)
-*/
- STACK(0x2A040000, 16K)
- PRERAM_CBFS_CACHE(0x2A044000, 93K)
- TTB_SUBTABLES(0x2A05B800, 2K)
- TTB(0x2A05C000, 16K)
- SRAM_END(0x2A060000)
-
- DRAM_START(0x40000000)
- RAMSTAGE(0x40640000, 128K)
- SYMBOL(memlayout_cbmem_top, 0x59F80000)
- POSTRAM_CBFS_CACHE(0x59F80000, 384K)
- DMA_COHERENT(0x5A000000, 2M)
+/* UBER_SBL(0x0A0C0000, 48K) */
+
+ PRERAM_CBFS_CACHE(0x0A0C0000, 93K)
+
+ TTB_SUBTABLES(0x0A0E0000, 4K)
+ TTB(0x0A0F0000, 16K)
+ REGION_END(wifi_imem_0, 0x0A100000)
+ /* ==^^^== WIFI_IMEM_0_END 0x0A100000 ==^^^== */
+
+
+ /* ==vvv== WIFI_IMEM_1_START 0x0A8C0000 ==vvv== */
+ REGION_START(wifi_imem_1, 0x0A8C0000)
+ BOOTBLOCK(0x0A8C0000, 24K)
+ OVERLAP_VERSTAGE_ROMSTAGE(0x0A8C6000, 64K)
+ VBOOT2_WORK(0x0A8D6000, 16K)
+ PRERAM_CBMEM_CONSOLE(0x0A8DA000, 32K)
+ TIMESTAMP(0x0A8E2000, 1K)
+
+/* 0x0A8E2400..0x0A8FC000 103 KB free */
+
+ STACK(0x0A8FC000, 16K)
+ REGION_END(wifi_imem_1, 0x0A900000)
+ /* ==^^^== WIFI_IMEM_1_END 0x0A900000 ==^^^== */
+
+ DRAM_START(0x80000000)
+ RAMSTAGE(0x80640000, 128K)
+ SYMBOL(memlayout_cbmem_top, 0x89F80000)
+ POSTRAM_CBFS_CACHE(0x89F80000, 384K)
+ DMA_COHERENT(0x8A000000, 2M)
}