diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-11-06 12:07:05 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-08 07:51:18 +0000 |
| commit | 056fbe49ff9cccc7646371452431a05b47544057 (patch) | |
| tree | 4bc2ea46dae5de31731678ba2eb86fa698034a3c /src/soc | |
| parent | c86fc8e63d81251a5da80ed55e4fbc9900a900d9 (diff) | |
ELOG, soc/intel: Avoid some preprocessor use
Change-Id: I5378573f37daa4f09db332023027deda677c7aeb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36646
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/baytrail/include/soc/pmc.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/smm.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/braswell/include/soc/pm.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/braswell/smm.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/include/soc/pmc.h | 10 | ||||
| -rw-r--r-- | src/soc/intel/fsp_baytrail/include/soc/pmc.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/fsp_baytrail/smm.c | 3 |
7 files changed, 6 insertions, 25 deletions
diff --git a/src/soc/intel/baytrail/include/soc/pmc.h b/src/soc/intel/baytrail/include/soc/pmc.h index 09d13221b3..6cdf419042 100644 --- a/src/soc/intel/baytrail/include/soc/pmc.h +++ b/src/soc/intel/baytrail/include/soc/pmc.h @@ -281,11 +281,7 @@ void enable_gpe(uint32_t mask); void disable_gpe(uint32_t mask); void disable_all_gpe(void); -#if CONFIG(ELOG) void southcluster_log_state(void); -#else -static inline void southcluster_log_state(void) {} -#endif /* Return non-zero when RTC failure happened. */ int rtc_failure(void); diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index 4f019229e4..9f10f70b61 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -38,7 +38,8 @@ void smm_southbridge_clear_state(void) uint32_t smi_en; /* Log events from chipset before clearing */ - southcluster_log_state(); + if (CONFIG(ELOG)) + southcluster_log_state(); printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase()); diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index 5063342955..744fcf085f 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -242,11 +242,7 @@ void enable_gpe(uint32_t mask); void disable_gpe(uint32_t mask); void disable_all_gpe(void); -#if CONFIG(ELOG) void southcluster_log_state(void); -#else -static inline void southcluster_log_state(void) {} -#endif /* Return non-zero when RTC failure happened. */ int rtc_failure(void); diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c index 364cda5b5a..c108a3629e 100644 --- a/src/soc/intel/braswell/smm.c +++ b/src/soc/intel/braswell/smm.c @@ -39,7 +39,8 @@ void smm_southbridge_clear_state(void) uint32_t smi_en; /* Log events from chipset before clearing */ - southcluster_log_state(); + if (CONFIG(ELOG)) + southcluster_log_state(); printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase()); diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h index af840a2f1a..62201d97a7 100644 --- a/src/soc/intel/denverton_ns/include/soc/pmc.h +++ b/src/soc/intel/denverton_ns/include/soc/pmc.h @@ -262,14 +262,4 @@ #define RST_CPU (1 << 2) #define SYS_RST (1 << 1) -#if !defined(__ASSEMBLER__) && !defined(__ACPI__) - -#if CONFIG(ELOG) -void southcluster_log_state(void); -#else -static inline void southcluster_log_state(void) {} -#endif - -#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ - #endif /* _DENVERTON_NS_PMC_H_ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/pmc.h b/src/soc/intel/fsp_baytrail/include/soc/pmc.h index 71c8e10446..9e588addae 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/pmc.h +++ b/src/soc/intel/fsp_baytrail/include/soc/pmc.h @@ -285,11 +285,7 @@ void disable_all_gpe(void); uint32_t chipset_prev_sleep_state(uint32_t clear); -#if CONFIG(ELOG) void southcluster_log_state(void); -#else -static inline void southcluster_log_state(void) {} -#endif #endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ diff --git a/src/soc/intel/fsp_baytrail/smm.c b/src/soc/intel/fsp_baytrail/smm.c index 0c40429aae..fbfd094c93 100644 --- a/src/soc/intel/fsp_baytrail/smm.c +++ b/src/soc/intel/fsp_baytrail/smm.c @@ -40,7 +40,8 @@ void smm_southbridge_clear_state(void) uint32_t smi_en; /* Log events from chipset before clearing */ - southcluster_log_state(); + if (CONFIG(ELOG)) + southcluster_log_state(); printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase()); |