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authorDuncan Laurie <dlaurie@chromium.org>2014-08-11 09:54:19 -0700
committerMarc Jones <marc.jones@se-eng.com>2015-03-27 05:40:39 +0100
commit047f03ab548ba298c01cbdb1fc64cbde8e1122ce (patch)
tree1170be68b30c95a50b71f90ff959514b599e4a6b /src/soc
parent17b786630fcd49eef46e9df7a18f8f8fb36d5308 (diff)
broadwell: Fix TCO register size and event reporting
TCO registers are 16bit not 32bit. Also do not log the TCO reset event in S3 resume path to avoid it being logged when TCO is not actually tripping. BUG=chrome-os-partner:28234 BRANCH=None TEST=manual: 1) build and boot on samus 2) modify kernel command line with nmi_watchdog=0 3) while sleep 1 ; do echo -n V ; done > /dev/watchdog & 4) fg 1 5) ctrl-Z 6) wait for reboot 7) check event log for TCO event 8) check suspend/resume path to ensure no TCO event logged Original-Change-Id: I9cd8627de8498b280deb088f3a8e1e20546e2f96 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211840 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 5952fe4672d07bd39e345f2048c2bfc510bf9f2a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I6cdeffb8b50c5001d714edd3a1264cf117cd1ad6 Reviewed-on: http://review.coreboot.org/8954 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/broadwell/broadwell/pm.h4
-rw-r--r--src/soc/intel/broadwell/elog.c5
-rw-r--r--src/soc/intel/broadwell/romstage/power_state.c7
3 files changed, 9 insertions, 7 deletions
diff --git a/src/soc/intel/broadwell/broadwell/pm.h b/src/soc/intel/broadwell/broadwell/pm.h
index b2810f0ca7..91f55fe1fb 100644
--- a/src/soc/intel/broadwell/broadwell/pm.h
+++ b/src/soc/intel/broadwell/broadwell/pm.h
@@ -123,8 +123,8 @@ struct chipset_power_state {
uint16_t pm1_sts;
uint16_t pm1_en;
uint32_t pm1_cnt;
- uint32_t tco1_sts;
- uint32_t tco2_sts;
+ uint16_t tco1_sts;
+ uint16_t tco2_sts;
uint32_t gpe0_sts[4];
uint32_t gpe0_en[4];
uint16_t gen_pmcon1;
diff --git a/src/soc/intel/broadwell/elog.c b/src/soc/intel/broadwell/elog.c
index 79484a9606..bb7e7ba4d2 100644
--- a/src/soc/intel/broadwell/elog.c
+++ b/src/soc/intel/broadwell/elog.c
@@ -91,8 +91,9 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps)
if (ps->gen_pmcon2 & PWROK_FLR)
elog_add_event(ELOG_TYPE_PWROK_FAIL);
- /* Second TCO Timeout */
- if (ps->tco2_sts & TCO2_STS_SECOND_TO)
+ /* TCO Timeout */
+ if (ps->prev_sleep_state != 3 &&
+ ps->tco2_sts & TCO2_STS_SECOND_TO)
elog_add_event(ELOG_TYPE_TCO_RESET);
/* Power Button Override */
diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/romstage/power_state.c
index 6e333c1d9e..7aa6177810 100644
--- a/src/soc/intel/broadwell/romstage/power_state.c
+++ b/src/soc/intel/broadwell/romstage/power_state.c
@@ -84,7 +84,8 @@ static void dump_power_state(struct chipset_power_state *ps)
printk(BIOS_DEBUG, "PM1_STS: %04x\n", ps->pm1_sts);
printk(BIOS_DEBUG, "PM1_EN: %04x\n", ps->pm1_en);
printk(BIOS_DEBUG, "PM1_CNT: %08x\n", ps->pm1_cnt);
- printk(BIOS_DEBUG, "TCO_STS: %08x %08x\n", ps->tco1_sts, ps->tco2_sts);
+ printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n",
+ ps->tco1_sts, ps->tco2_sts);
printk(BIOS_DEBUG, "GPE0_STS: %08x %08x %08x %08x\n",
ps->gpe0_sts[0], ps->gpe0_sts[1],
@@ -108,8 +109,8 @@ struct chipset_power_state *fill_power_state(void)
ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
- ps->tco1_sts = inl(ACPI_BASE_ADDRESS + TCO1_STS);
- ps->tco2_sts = inl(ACPI_BASE_ADDRESS + TCO2_STS);
+ ps->tco1_sts = inw(ACPI_BASE_ADDRESS + TCO1_STS);
+ ps->tco2_sts = inw(ACPI_BASE_ADDRESS + TCO2_STS);
ps->gpe0_sts[0] = inl(ACPI_BASE_ADDRESS + GPE0_STS(0));
ps->gpe0_sts[1] = inl(ACPI_BASE_ADDRESS + GPE0_STS(1));
ps->gpe0_sts[2] = inl(ACPI_BASE_ADDRESS + GPE0_STS(2));