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authorElyes HAOUAS <ehaouas@noos.fr>2018-10-27 16:40:25 +0200
committerNico Huber <nico.h@gmx.de>2019-03-29 20:00:20 +0000
commiteb789f0b79aa99e214ccefc04f9f78b550f52f32 (patch)
tree59f72703d67577e4aaf76e276ddd442b583cbc14 /src/soc
parent28fa33ccbce042d09daf64efa2097b67570ad4af (diff)
src: Use include <reset.h> when appropriate
Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/cavium/common/bdk-coreboot.c1
-rw-r--r--src/soc/intel/braswell/romstage/romstage.c1
-rw-r--r--src/soc/intel/common/block/cpu/cpulib.c1
-rw-r--r--src/soc/intel/fsp_baytrail/bootblock/bootblock.c1
-rw-r--r--src/soc/intel/skylake/romstage/romstage.c1
5 files changed, 0 insertions, 5 deletions
diff --git a/src/soc/cavium/common/bdk-coreboot.c b/src/soc/cavium/common/bdk-coreboot.c
index 066155e08e..f8fa8d499e 100644
--- a/src/soc/cavium/common/bdk-coreboot.c
+++ b/src/soc/cavium/common/bdk-coreboot.c
@@ -22,7 +22,6 @@
#include <device/i2c_simple.h>
#include <endian.h>
#include <delay.h>
-#include <reset.h>
#include <soc/timer.h>
// BDK
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index ca1eb40236..ae2eac8e20 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -31,7 +31,6 @@
#include <mrc_cache.h>
#include <string.h>
#include <timestamp.h>
-#include <reset.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <fsp/util.h>
#include <soc/gpio.h>
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c
index 61ad7edb74..9dbfbd47ee 100644
--- a/src/soc/intel/common/block/cpu/cpulib.c
+++ b/src/soc/intel/common/block/cpu/cpulib.c
@@ -24,7 +24,6 @@
#include <delay.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/fast_spi.h>
-#include <reset.h>
#include <soc/cpu.h>
#include <soc/iomap.h>
#include <soc/pm.h>
diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
index b471e5cf08..5351a0162f 100644
--- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
+++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
@@ -27,7 +27,6 @@
#include <soc/iomap.h>
#include <soc/lpc.h>
#include <soc/gpio.h>
-#include <reset.h>
/*
* check for a warm reset and do a hard reset instead.
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index ac43c27071..d8188f6924 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -26,7 +26,6 @@
#include <elog.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/pmclib.h>
-#include <reset.h>
#include <soc/pci_devs.h>
#include <soc/pei_wrapper.h>
#include <soc/pm.h>