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authorVanessa Eusebio <vanessa.f.eusebio@intel.com>2018-06-06 13:12:53 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-01-18 08:16:28 +0000
commitcd97982e2e2a9eaff50cc9dce02d7d5a18685583 (patch)
tree81b65aaa970da72345baf1a3d6efe5c7b5546aee /src/soc
parent2dfa53f80ecfbfe7e407a44af20a562f35faedd8 (diff)
soc/intel/denverton_ns: Select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
* Add CPU_INTEL_FIRMWARE_INTERFACE_TABLE Change-Id: I9d4901ea56d5bf5225a8f3a6015d2ea80a9e46b5 Signed-off-by: Vanessa Eusebio <vanessa.f.eusebio@intel.com> Reviewed-on: https://review.coreboot.org/c/26928 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/denverton_ns/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index 1096549461..e34e4d1b85 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -56,6 +56,7 @@ config CPU_SPECIFIC_OPTIONS
select TSC_SYNC_MFENCE
select UDELAY_TSC
select UDK_2015_BINDING
+ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
config FSP_T_ADDR
hex "Intel FSP-T (temp ram init) binary location"