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authorAlexandru Gagniuc <alexandrux.gagniuc@intel.com>2016-04-28 10:38:05 -0700
committerMartin Roth <martinroth@google.com>2016-05-06 18:56:22 +0200
commitbdd921c7720d372399ab57796eb9dcba48530249 (patch)
tree37aea30ec1055d2421df91c0110656b6ee4a0b42 /src/soc
parente237f8b766971ffb604eaeb29a14a7769a96f830 (diff)
soc/apollolake/lpc_lib: Add utility to configure LPC pads
Change-Id: Iaf325863681ad9b8b5d7662a9d267488b8fdf008 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14587 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/apollolake/include/soc/lpc.h2
-rw-r--r--src/soc/intel/apollolake/lpc_lib.c16
2 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/lpc.h b/src/soc/intel/apollolake/include/soc/lpc.h
index 9a1c397d8e..7e3d74aaf6 100644
--- a/src/soc/intel/apollolake/include/soc/lpc.h
+++ b/src/soc/intel/apollolake/include/soc/lpc.h
@@ -53,6 +53,8 @@
#define LGMR_EN (1 << 0)
#define LGMR_WINDOW_SIZE (64 * KiB)
+/* Configure the SOC's LPC pads and mux them to the LPC function. */
+void lpc_configure_pads(void);
/* Enable fixed IO ranges to LPC. IOE_* macros can be OR'ed together. */
void lpc_enable_fixed_io_ranges(uint16_t io_enables);
/* Open a generic IO window to the LPC bus. Four windows are available. */
diff --git a/src/soc/intel/apollolake/lpc_lib.c b/src/soc/intel/apollolake/lpc_lib.c
index 14e052eace..654c83e838 100644
--- a/src/soc/intel/apollolake/lpc_lib.c
+++ b/src/soc/intel/apollolake/lpc_lib.c
@@ -20,6 +20,7 @@
#include <console/console.h>
#include <device/pci.h>
#include <lib.h>
+#include <soc/gpio.h>
#include <soc/lpc.h>
#include <soc/pci_devs.h>
@@ -44,6 +45,21 @@ static const struct lpc_mmio_range {
{ 0, 0 }
};
+static const struct pad_config lpc_gpios[] = {
+ PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(LPC_CLKOUT0, UP_20K, DEEP, NF1),
+ PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
+};
+
+void lpc_configure_pads(void)
+{
+ gpio_configure_pads(lpc_gpios, ARRAY_SIZE(lpc_gpios));
+}
+
void lpc_enable_fixed_io_ranges(uint16_t io_enables)
{
uint16_t reg_io_enables;