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authorJamie Ryu <jamie.m.ryu@intel.com>2020-06-24 18:29:06 -0700
committerTim Wawrzynczak <twawrzynczak@chromium.org>2020-07-01 17:25:35 +0000
commitbd8e761be20c08e56fd79e357727101def0ff622 (patch)
treec5ae2447c01daed773d4e4eecf92b7e07ff0c62d /src/soc
parentbc76cf56a4742cfb221ca1770e36af22e910ee77 (diff)
soc/intel/tigerlake: Switch to CSE Lite RW at BS_DEV_INIT_CHIPS entry
This is a W/A to avoid a communication issue with CSE Lite over Heci interface. This will help to avoid boot failures with CSE Lite until the permanent fix is available. BUG=b:159884143 TEST=build and boot volteer with serial and non-serial image Change-Id: Ib136a2154b36c63c7147bbcfbf1ca7beac3a5685 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42790 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/intel/common/block/cse/cse_lite.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index 3077c7f09e..8e43e35c47 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -361,4 +361,8 @@ void cse_fw_sync(void *unused)
}
}
+#if CONFIG(SOC_INTEL_TIGERLAKE)
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, cse_fw_sync, NULL);
+#else
BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, cse_fw_sync, NULL);
+#endif