diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-29 23:14:53 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-02-06 07:16:16 +0000 |
| commit | 8fee9951d30d03b4bca16c198b887c5415418c12 (patch) | |
| tree | 929be61cb85aee7c83bcc4e91f82ef379e960b60 /src/soc | |
| parent | 68d68f1d7c7693f7e49634b6c2106d3c2630d4b0 (diff) | |
sb,soc/intel: Add wake source fields in GNVS
For the moment, these are most not used but become a necessity
for a unified <soc/nvs.h> approach.
They would be required for the implementation of _SWS method
for OSPM to determine the reason for system waking up. The related
hardware registers are present with these platforms.
It's expected that ACPI power-management related GNVS entries are
grouped together to form a single struct in later works.
Change-Id: I6d31d39ac1017cd6fdf0ac66b418d1fbb1edf8e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50193
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/baytrail/acpi/globalnvs.asl | 1 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/include/soc/nvs.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/quark/include/soc/nvs.h | 4 |
3 files changed, 7 insertions, 1 deletions
diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index cffb2241f0..c73b7a7b3f 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -25,6 +25,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) TLVL, 8, /* 0x13 - Throttle Level */ PPCM, 8, /* 0x14 - Maximum P-state usable by OS */ PM1I, 32, /* 0x15 - System Wake Source - PM1 Index */ + GPEI, 32, /* 0x19 - GPE Wake Source */ /* Device Config */ Offset (0x20), diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h index 9fb0822b9b..a068d1edd4 100644 --- a/src/soc/intel/baytrail/include/soc/nvs.h +++ b/src/soc/intel/baytrail/include/soc/nvs.h @@ -25,7 +25,8 @@ struct __packed global_nvs { u8 tlvl; /* 0x13 - Throttle Level */ u8 ppcm; /* 0x14 - Maximum P-state usable by OS */ u32 pm1i; /* 0x15 - System Wake Source - PM1 Index */ - u8 rsvd1[7]; + u32 gpei; /* 0x19 - GPE Wake Source */ + u8 rsvd1[3]; /* Device Config */ u8 s5u0; /* 0x20 - Enable USB0 in S5 */ diff --git a/src/soc/intel/quark/include/soc/nvs.h b/src/soc/intel/quark/include/soc/nvs.h index fee0e42a7d..64378cce3d 100644 --- a/src/soc/intel/quark/include/soc/nvs.h +++ b/src/soc/intel/quark/include/soc/nvs.h @@ -8,6 +8,10 @@ struct __packed global_nvs { uint32_t cbmc; /* 0x00 - 0x03 - coreboot Memory Console */ uint8_t pwrs; /* 0x4 - Power state (AC = 1) */ + + /* Required for future unified acpi_save_wake_source. */ + uint32_t pm1i; + uint32_t gpei; }; #endif /* SOC_INTEL_QUARK_NVS_H */ |